Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Tue Feb 18 10:38:45 2025
| Host              : teddy01.fnal.gov running 64-bit AlmaLinux 9.5 (Teal Serval)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu49dr-ffvf1760
| Speed File        : -2  PRODUCTION 1.32 01-31-2021
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                                                                            Violations  
---------  --------  -----------------------------------------------------------------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                                                                           24          
TIMING-9   Warning   Unknown CDC Logic                                                                                      1           
TIMING-10  Warning   Missing property on synchronizer                                                                       1           
TIMING-18  Warning   Missing input or output delay                                                                          10          
TIMING-24  Warning   Overridden Max delay datapath only                                                                     12          
TIMING-47  Warning   False path, asynchronous clock group or max delay datapath only constraint between synchronous clocks  2           
CLKC-40    Advisory  Substitute PLLE4 for MMCME4 check                                                                      1           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC                                                             1           
XDCB-6     Advisory  Timing constraint pointing to hierarchical pins                                                        1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (2)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (2)
------------------------------
 There are 2 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.034        0.000                      0               703378        0.010        0.000                      0               702844        0.000        0.000                       0                250909  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                                ------------           ----------      --------------
RFADC0_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC1_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC2_CLK                                                                                           {0.000 2.034}          4.069           245.761         
RFADC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFDAC0_CLK                                                                                           {0.000 1.018}          2.035           491.400         
RFDAC1_CLK                                                                                           {0.000 1.018}          2.035           491.400         
RFDAC2_CLK                                                                                           {0.000 1.018}          2.035           491.400         
RFDAC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
clk_pl_0                                                                                             {0.000 5.000}          10.000          100.000         
  clk_out1_d_1_clk_core_0                                                                            {0.000 2.500}          5.000           200.000         
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {0.000 25.000}         50.000          20.000          
default_sysclk_c0_300mhz_clk_p                                                                       {0.000 1.667}          3.334           299.940         
  mmcm_clkout0                                                                                       {0.000 1.500}          3.001           333.267         
    pll_clk[0]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[0]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[1]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[1]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
  mmcm_clkout5                                                                                       {0.000 6.001}          12.002          83.317          
  mmcm_clkout6                                                                                       {0.000 3.001}          6.001           166.633         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC2_CLK                                                                                                 0.199        0.000                      0               128633        0.010        0.000                      0               128633        1.384        0.000                       0                 40844  
RFDAC2_CLK                                                                                                 0.034        0.000                      0               316630        0.010        0.000                      0               316630        0.377        0.000                       0                122497  
clk_pl_0                                                                                                   1.534        0.000                      0               163676        0.010        0.000                      0               163676        2.000        0.000                       0                 53450  
  clk_out1_d_1_clk_core_0                                                                                  0.336        0.000                      0                13353        0.019        0.000                      0                13353        1.958        0.000                       0                  4245  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       12.699        0.000                      0                  992        0.028        0.000                      0                  992       24.468        0.000                       0                   479  
default_sysclk_c0_300mhz_clk_p                                                                             1.969        0.000                      0                   23        0.042        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                             0.038        0.000                      0                70192        0.011        0.000                      0                70192        0.000        0.000                       0                 27078  
    pll_clk[0]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                         0.000        0.000                       0                     8  
      pll_clk[1]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    27  
  mmcm_clkout5                                                                                             9.924        0.000                      0                  827        0.015        0.000                      0                  827        5.469        0.000                       0                   570  
  mmcm_clkout6                                                                                             1.496        0.000                      0                 5376        0.023        0.000                      0                 5046        1.009        0.000                       0                  1643  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.618        0.000                      0                    8                                                                        
mmcm_clkout5                                                                                         mmcm_clkout0                                                                                               2.508        0.000                      0                   28                                                                        
mmcm_clkout6                                                                                         mmcm_clkout0                                                                                               1.755        0.000                      0                  115                                                                        
mmcm_clkout0                                                                                         pll_clk[0]_DIV                                                                                             0.739        0.000                      0                  352        0.531        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[1]_DIV                                                                                             0.705        0.000                      0                  236        0.572        0.000                      0                  236  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                              49.536        0.000                      0                    8                                                                        
mmcm_clkout0                                                                                         mmcm_clkout5                                                                                              11.567        0.000                      0                   10                                                                        
mmcm_clkout0                                                                                         mmcm_clkout6                                                                                               1.446        0.000                      0                   36        0.151        0.000                      0                    1  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           ----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                    RFADC2_CLK                                                                                           RFADC2_CLK                                                                                                 2.101        0.000                      0                    4        0.261        0.000                      0                    4  
**async_default**                                                                                    clk_out1_d_1_clk_core_0                                                                              clk_out1_d_1_clk_core_0                                                                                    2.279        0.000                      0                 2032        1.013        0.000                      0                 2032  
**async_default**                                                                                    clk_pl_0                                                                                             clk_pl_0                                                                                                   7.252        0.000                      0                  642        0.149        0.000                      0                  642  
**async_default**                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       48.651        0.000                      0                  100        0.094        0.000                      0                  100  
**async_default**                                                                                    mmcm_clkout5                                                                                         mmcm_clkout5                                                                                              10.833        0.000                      0                  105        0.126        0.000                      0                  105  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                                                                                                                                
(none)                                                                                                                                                                                                    RFADC2_CLK                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                           RFADC2_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFADC2_CLK                                                                                           
(none)                                                                                               mmcm_clkout0                                                                                         RFADC2_CLK                                                                                           
(none)                                                                                                                                                                                                    RFDAC2_CLK                                                                                           
(none)                                                                                               RFADC2_CLK                                                                                           RFDAC2_CLK                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                           RFDAC2_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              RFDAC2_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFDAC2_CLK                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                           clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                               RFADC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              clk_pl_0                                                                                             
(none)                                                                                               clk_pl_0                                                                                             clk_pl_0                                                                                             
(none)                                                                                               mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                               clk_pl_0                                                                                             default_sysclk_c0_300mhz_clk_p                                                                       
(none)                                                                                               RFADC2_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               RFDAC2_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_pl_0                                                                                             mmcm_clkout0                                                                                         
(none)                                                                                               default_sysclk_c0_300mhz_clk_p                                                                       mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout5                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout5                                                                                         
(none)                                                                                               default_sysclk_c0_300mhz_clk_p                                                                       mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout6                                                                                         


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               clk_pl_0                                                                                                                                                                                                  
(none)                                                                                               mmcm_clkout0                                                                                                                                                                                              
(none)                                                                                                                                                                                                    RFDAC2_CLK                                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                                                                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                                                                                                                                    default_sysclk_c0_300mhz_clk_p                                                                       


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC2_CLK
  To Clock:  RFADC2_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.199ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.384ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.199ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_20/ADDRARDADDR[13]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.678ns  (logic 0.079ns (2.148%)  route 3.599ns (97.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.671ns = ( 6.740 - 4.069 ) 
    Source Clock Delay      (SCD):    2.803ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 1.062ns, distribution 1.215ns)
  Clock Net Delay (Destination): 2.285ns (routing 0.960ns, distribution 1.325ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.277     2.803    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X47Y204        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y204        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.882 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/Q
                         net (fo=32, routed)          3.599     6.481    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[9]
    RAMB36_X0Y52         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_20/ADDRARDADDR[13]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.285     6.740    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X0Y52         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_20/CLKARDCLK
                         clock pessimism              0.250     6.990    
                         clock uncertainty           -0.035     6.955    
    RAMB36_X0Y52         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[13])
                                                     -0.274     6.681    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_20
  -------------------------------------------------------------------
                         required time                          6.681    
                         arrival time                          -6.481    
  -------------------------------------------------------------------
                         slack                                  0.199    

Slack (MET) :             0.222ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_22/ADDRARDADDR[13]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.643ns  (logic 0.079ns (2.168%)  route 3.564ns (97.832%))
  Logic Levels:           0  
  Clock Path Skew:        0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.659ns = ( 6.728 - 4.069 ) 
    Source Clock Delay      (SCD):    2.803ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 1.062ns, distribution 1.215ns)
  Clock Net Delay (Destination): 2.273ns (routing 0.960ns, distribution 1.313ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.277     2.803    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X47Y204        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y204        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.882 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/Q
                         net (fo=32, routed)          3.564     6.447    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[9]
    RAMB36_X0Y54         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_22/ADDRARDADDR[13]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.273     6.728    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X0Y54         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_22/CLKARDCLK
                         clock pessimism              0.250     6.978    
                         clock uncertainty           -0.035     6.943    
    RAMB36_X0Y54         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[13])
                                                     -0.274     6.669    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_22
  -------------------------------------------------------------------
                         required time                          6.669    
                         arrival time                          -6.447    
  -------------------------------------------------------------------
                         slack                                  0.222    

Slack (MET) :             0.262ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_6/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.580ns  (logic 0.078ns (2.179%)  route 3.502ns (97.821%))
  Logic Levels:           0  
  Clock Path Skew:        0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.654ns = ( 6.723 - 4.069 ) 
    Source Clock Delay      (SCD):    2.811ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.285ns (routing 1.062ns, distribution 1.223ns)
  Clock Net Delay (Destination): 2.268ns (routing 0.960ns, distribution 1.308ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.285     2.811    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X48Y239        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y239        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.889 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/Q
                         net (fo=35, routed)          3.502     6.391    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[1]
    RAMB36_X1Y62         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_6/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.268     6.723    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X1Y62         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_6/CLKARDCLK
                         clock pessimism              0.250     6.973    
                         clock uncertainty           -0.035     6.938    
    RAMB36_X1Y62         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.285     6.653    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_6
  -------------------------------------------------------------------
                         required time                          6.653    
                         arrival time                          -6.391    
  -------------------------------------------------------------------
                         slack                                  0.262    

Slack (MET) :             0.324ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_7/ADDRARDADDR[8]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.502ns  (logic 0.078ns (2.227%)  route 3.424ns (97.773%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.650ns = ( 6.719 - 4.069 ) 
    Source Clock Delay      (SCD):    2.841ns
    Clock Pessimism Removal (CPR):    0.267ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.315ns (routing 1.062ns, distribution 1.253ns)
  Clock Net Delay (Destination): 2.264ns (routing 0.960ns, distribution 1.304ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.315     2.841    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X48Y241        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y241        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     2.919 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/Q
                         net (fo=33, routed)          3.424     6.343    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[3]
    RAMB36_X1Y63         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_7/ADDRARDADDR[8]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.264     6.719    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X1Y63         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_7/CLKARDCLK
                         clock pessimism              0.267     6.986    
                         clock uncertainty           -0.035     6.951    
    RAMB36_X1Y63         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[8])
                                                     -0.283     6.668    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_7
  -------------------------------------------------------------------
                         required time                          6.668    
                         arrival time                          -6.343    
  -------------------------------------------------------------------
                         slack                                  0.324    

Slack (MET) :             0.327ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_23/ADDRARDADDR[13]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.544ns  (logic 0.079ns (2.229%)  route 3.465ns (97.771%))
  Logic Levels:           0  
  Clock Path Skew:        0.112ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.665ns = ( 6.734 - 4.069 ) 
    Source Clock Delay      (SCD):    2.803ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 1.062ns, distribution 1.215ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.960ns, distribution 1.319ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.277     2.803    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X47Y204        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y204        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.882 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/Q
                         net (fo=32, routed)          3.465     6.348    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[9]
    RAMB36_X0Y55         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_23/ADDRARDADDR[13]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.279     6.734    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X0Y55         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_23/CLKARDCLK
                         clock pessimism              0.250     6.984    
                         clock uncertainty           -0.035     6.949    
    RAMB36_X0Y55         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[13])
                                                     -0.274     6.675    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_23
  -------------------------------------------------------------------
                         required time                          6.675    
                         arrival time                          -6.348    
  -------------------------------------------------------------------
                         slack                                  0.327    

Slack (MET) :             0.354ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_3/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.469ns  (logic 0.078ns (2.249%)  route 3.391ns (97.751%))
  Logic Levels:           0  
  Clock Path Skew:        0.074ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.635ns = ( 6.704 - 4.069 ) 
    Source Clock Delay      (SCD):    2.811ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.285ns (routing 1.062ns, distribution 1.223ns)
  Clock Net Delay (Destination): 2.249ns (routing 0.960ns, distribution 1.289ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.285     2.811    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X48Y239        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y239        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.889 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/Q
                         net (fo=35, routed)          3.391     6.280    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[1]
    RAMB36_X1Y59         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_3/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.249     6.704    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X1Y59         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_3/CLKARDCLK
                         clock pessimism              0.250     6.954    
                         clock uncertainty           -0.035     6.919    
    RAMB36_X1Y59         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.285     6.634    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_3
  -------------------------------------------------------------------
                         required time                          6.634    
                         arrival time                          -6.280    
  -------------------------------------------------------------------
                         slack                                  0.354    

Slack (MET) :             0.367ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_5/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.477ns  (logic 0.078ns (2.243%)  route 3.399ns (97.757%))
  Logic Levels:           0  
  Clock Path Skew:        0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.656ns = ( 6.725 - 4.069 ) 
    Source Clock Delay      (SCD):    2.811ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.285ns (routing 1.062ns, distribution 1.223ns)
  Clock Net Delay (Destination): 2.270ns (routing 0.960ns, distribution 1.310ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.285     2.811    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X48Y239        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y239        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.889 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/Q
                         net (fo=35, routed)          3.399     6.288    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[1]
    RAMB36_X1Y61         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_5/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.270     6.725    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X1Y61         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_5/CLKARDCLK
                         clock pessimism              0.250     6.975    
                         clock uncertainty           -0.035     6.940    
    RAMB36_X1Y61         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.285     6.655    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_5
  -------------------------------------------------------------------
                         required time                          6.655    
                         arrival time                          -6.288    
  -------------------------------------------------------------------
                         slack                                  0.367    

Slack (MET) :             0.383ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_4/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.461ns  (logic 0.078ns (2.253%)  route 3.383ns (97.747%))
  Logic Levels:           0  
  Clock Path Skew:        0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.657ns = ( 6.726 - 4.069 ) 
    Source Clock Delay      (SCD):    2.811ns
    Clock Pessimism Removal (CPR):    0.250ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.285ns (routing 1.062ns, distribution 1.223ns)
  Clock Net Delay (Destination): 2.271ns (routing 0.960ns, distribution 1.311ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.285     2.811    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X48Y239        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y239        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.889 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]/Q
                         net (fo=35, routed)          3.383     6.272    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[1]
    RAMB36_X1Y60         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_4/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.271     6.726    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X1Y60         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_4/CLKARDCLK
                         clock pessimism              0.250     6.976    
                         clock uncertainty           -0.035     6.941    
    RAMB36_X1Y60         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.285     6.656    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_4
  -------------------------------------------------------------------
                         required time                          6.656    
                         arrival time                          -6.272    
  -------------------------------------------------------------------
                         slack                                  0.383    

Slack (MET) :             0.391ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[6]/DSP_A_B_DATA_INST/B[4]
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.028ns  (logic 0.327ns (10.800%)  route 2.701ns (89.200%))
  Logic Levels:           0  
  Clock Path Skew:        -0.351ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.510ns = ( 6.579 - 4.069 ) 
    Source Clock Delay      (SCD):    3.178ns
    Clock Pessimism Removal (CPR):    0.317ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.652ns (routing 1.062ns, distribution 1.590ns)
  Clock Net Delay (Destination): 2.124ns (routing 0.960ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.652     3.178    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m2_axis_aclk
    RFADC_X0Y2           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_FABRIC_CLK_DATA_ADC2[100])
                                                      0.327     3.505 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DATA_ADC2[100]
                         net (fo=3, routed)           2.701     6.206    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[6]/B[4]
    DSP48E2_X14Y60       DSP_A_B_DATA                                 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[6]/DSP_A_B_DATA_INST/B[4]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.124     6.579    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[6]/CLK
    DSP48E2_X14Y60       DSP_A_B_DATA                                 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[6]/DSP_A_B_DATA_INST/CLK
                         clock pessimism              0.317     6.896    
                         clock uncertainty           -0.035     6.861    
    DSP48E2_X14Y60       DSP_A_B_DATA (Setup_DSP_A_B_DATA_DSP48E2_CLK_B[4])
                                                     -0.264     6.597    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[6]/DSP_A_B_DATA_INST
  -------------------------------------------------------------------
                         required time                          6.597    
                         arrival time                          -6.206    
  -------------------------------------------------------------------
                         slack                                  0.391    

Slack (MET) :             0.391ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/ADDRARDADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        3.494ns  (logic 0.079ns (2.261%)  route 3.415ns (97.739%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.694ns = ( 6.763 - 4.069 ) 
    Source Clock Delay      (SCD):    2.833ns
    Clock Pessimism Removal (CPR):    0.267ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.307ns (routing 1.062ns, distribution 1.245ns)
  Clock Net Delay (Destination): 2.308ns (routing 0.960ns, distribution 1.348ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.307     2.833    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X47Y245        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y245        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.912 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/Q
                         net (fo=32, routed)          3.415     6.327    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[4]
    RAMB36_X0Y63         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/ADDRARDADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.308     6.763    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X0Y63         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
                         clock pessimism              0.267     7.030    
                         clock uncertainty           -0.035     6.995    
    RAMB36_X0Y63         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[9])
                                                     -0.277     6.718    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15
  -------------------------------------------------------------------
                         required time                          6.718    
                         arrival time                          -6.327    
  -------------------------------------------------------------------
                         slack                                  0.391    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.244ns  (logic 0.058ns (23.771%)  route 0.186ns (76.230%))
  Logic Levels:           0  
  Clock Path Skew:        0.202ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.952ns
    Source Clock Delay      (SCD):    2.504ns
    Clock Pessimism Removal (CPR):    0.246ns
  Clock Net Delay (Source):      2.118ns (routing 0.960ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.426ns (routing 1.062ns, distribution 1.364ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.118     2.504    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X70Y114        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y114        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.562 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.186     2.748    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X70Y123        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.426     2.952    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X70Y123        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.246     2.706    
    SLICE_X70Y123        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.738    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.738    
                         arrival time                           2.748    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[50].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.059ns (45.385%)  route 0.071ns (54.615%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.977ns
    Source Clock Delay      (SCD):    2.544ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Net Delay (Source):      2.158ns (routing 0.960ns, distribution 1.198ns)
  Clock Net Delay (Destination): 2.451ns (routing 1.062ns, distribution 1.389ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.158     2.544    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[50].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X77Y18         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[50].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y18         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.603 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[50].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/Q
                         net (fo=2, routed)           0.071     2.674    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]_1
    SLICE_X77Y16         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.451     2.977    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X77Y16         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]/C
                         clock pessimism             -0.375     2.602    
    SLICE_X77Y16         FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     2.664    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.664    
                         arrival time                           2.674    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.198ns  (logic 0.061ns (30.808%)  route 0.137ns (69.192%))
  Logic Levels:           0  
  Clock Path Skew:        0.158ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.989ns
    Source Clock Delay      (SCD):    2.509ns
    Clock Pessimism Removal (CPR):    0.322ns
  Clock Net Delay (Source):      2.123ns (routing 0.960ns, distribution 1.163ns)
  Clock Net Delay (Destination): 2.463ns (routing 1.062ns, distribution 1.401ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.123     2.509    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X66Y48         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y48         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     2.570 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/Q
                         net (fo=1, routed)           0.137     2.707    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[0]
    SLICE_X67Y53         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.463     2.989    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X67Y53         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/CLK
                         clock pessimism             -0.322     2.667    
    SLICE_X67Y53         SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.029     2.696    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2
  -------------------------------------------------------------------
                         required time                         -2.696    
                         arrival time                           2.707    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.126ns  (logic 0.059ns (46.825%)  route 0.067ns (53.175%))
  Logic Levels:           0  
  Clock Path Skew:        0.083ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.986ns
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Net Delay (Source):      2.135ns (routing 0.960ns, distribution 1.175ns)
  Clock Net Delay (Destination): 2.460ns (routing 1.062ns, distribution 1.398ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.135     2.521    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X71Y36         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y36         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.580 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/Q
                         net (fo=1, routed)           0.067     2.647    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_0
    SLICE_X70Y36         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.460     2.986    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X70Y36         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/CLK
                         clock pessimism             -0.383     2.604    
    SLICE_X70Y36         SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.636    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2
  -------------------------------------------------------------------
                         required time                         -2.636    
                         arrival time                           2.647    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.058ns (43.609%)  route 0.075ns (56.391%))
  Logic Levels:           0  
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.848ns
    Source Clock Delay      (SCD):    2.399ns
    Clock Pessimism Removal (CPR):    0.360ns
  Clock Net Delay (Source):      2.013ns (routing 0.960ns, distribution 1.053ns)
  Clock Net Delay (Destination): 2.322ns (routing 1.062ns, distribution 1.260ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.013     2.399    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X45Y104        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y104        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.457 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.075     2.532    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X45Y106        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.322     2.848    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X45Y106        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.360     2.488    
    SLICE_X45Y106        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.520    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[17].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.520    
                         arrival time                           2.532    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.058ns (43.609%)  route 0.075ns (56.391%))
  Logic Levels:           0  
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.844ns
    Source Clock Delay      (SCD):    2.395ns
    Clock Pessimism Removal (CPR):    0.360ns
  Clock Net Delay (Source):      2.009ns (routing 0.960ns, distribution 1.049ns)
  Clock Net Delay (Destination): 2.318ns (routing 1.062ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.009     2.395    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X45Y99         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y99         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.453 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.075     2.528    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X45Y101        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.318     2.844    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X45Y101        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.360     2.484    
    SLICE_X45Y101        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.516    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.516    
                         arrival time                           2.528    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[421]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.190ns  (logic 0.057ns (30.000%)  route 0.133ns (70.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.947ns
    Source Clock Delay      (SCD):    2.507ns
    Clock Pessimism Removal (CPR):    0.322ns
  Clock Net Delay (Source):      2.121ns (routing 0.960ns, distribution 1.161ns)
  Clock Net Delay (Destination): 2.421ns (routing 1.062ns, distribution 1.359ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.121     2.507    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X66Y54         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y54         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.564 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][29]/Q
                         net (fo=1, routed)           0.133     2.697    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_phase[5].phase_v1_r1_reg[5]_45[29]
    SLICE_X67Y55         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[421]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.421     2.947    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X67Y55         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[421]/C
                         clock pessimism             -0.322     2.625    
    SLICE_X67Y55         FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.060     2.685    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[421]
  -------------------------------------------------------------------
                         required time                         -2.685    
                         arrival time                           2.697    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_dout_r2_reg[0][14]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.285ns  (logic 0.058ns (20.359%)  route 0.227ns (79.641%))
  Logic Levels:           0  
  Clock Path Skew:        0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.952ns
    Source Clock Delay      (SCD):    2.481ns
    Clock Pessimism Removal (CPR):    0.246ns
  Clock Net Delay (Source):      2.095ns (routing 0.960ns, distribution 1.135ns)
  Clock Net Delay (Destination): 2.426ns (routing 1.062ns, distribution 1.364ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.095     2.481    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/aclk
    SLICE_X65Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y119        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.539 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[6]/Q
                         net (fo=2, routed)           0.227     2.766    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_dout[0]_0[14]
    SLICE_X67Y121        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_dout_r2_reg[0][14]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.426     2.952    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X67Y121        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_dout_r2_reg[0][14]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r/CLK
                         clock pessimism             -0.246     2.706    
    SLICE_X67Y121        SRL16E (Hold_G5LUT_SLICEM_CLK_D)
                                                      0.047     2.753    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_dout_r2_reg[0][14]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r
  -------------------------------------------------------------------
                         required time                         -2.753    
                         arrival time                           2.766    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.058ns (42.647%)  route 0.078ns (57.353%))
  Logic Levels:           0  
  Clock Path Skew:        0.095ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.020ns
    Source Clock Delay      (SCD):    2.553ns
    Clock Pessimism Removal (CPR):    0.372ns
  Clock Net Delay (Source):      2.167ns (routing 0.960ns, distribution 1.207ns)
  Clock Net Delay (Destination): 2.494ns (routing 1.062ns, distribution 1.432ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.167     2.553    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X76Y49         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y49         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     2.611 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][1]/Q
                         net (fo=1, routed)           0.078     2.689    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]
    SLICE_X76Y50         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.494     3.020    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X76Y50         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl6/CLK
                         clock pessimism             -0.372     2.648    
    SLICE_X76Y50         SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     2.677    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl6
  -------------------------------------------------------------------
                         required time                         -2.677    
                         arrival time                           2.689    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[21].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[29].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[28][13]_srl29/D
                            (rising edge-triggered cell SRLC32E clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.058ns (29.605%)  route 0.138ns (70.395%))
  Logic Levels:           0  
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.854ns
    Source Clock Delay      (SCD):    2.406ns
    Clock Pessimism Removal (CPR):    0.311ns
  Clock Net Delay (Source):      2.020ns (routing 0.960ns, distribution 1.060ns)
  Clock Net Delay (Destination): 2.328ns (routing 1.062ns, distribution 1.266ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.020     2.406    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[21].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X47Y72         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[21].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y72         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.464 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[21].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[13]/Q
                         net (fo=2, routed)           0.138     2.602    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[29].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[29][13]_0
    SLICE_X45Y71         SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[29].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[28][13]_srl29/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.328     2.854    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[29].i_data_casc_dly/aclk
    SLICE_X45Y71         SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[29].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[28][13]_srl29/CLK
                         clock pessimism             -0.311     2.543    
    SLICE_X45Y71         SRLC32E (Hold_G6LUT_SLICEM_CLK_D)
                                                      0.047     2.590    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[29].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[28][13]_srl29
  -------------------------------------------------------------------
                         required time                         -2.590    
                         arrival time                           2.602    
  -------------------------------------------------------------------
                         slack                                  0.013    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC2_CLK
Waveform(ns):       { 0.000 2.034 }
Period(ns):         4.069
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RFADC/FABRIC_CLK    n/a            1.626         4.069       2.443      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X1Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X1Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y40  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y41  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y42  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y43  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y44  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_14/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y45  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         4.069       2.714      RAMB36_X0Y48  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16/CLKARDCLK
Low Pulse Width   Slow    RFADC/FABRIC_CLK    n/a            0.650         2.035       1.385      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Fast    RFADC/FABRIC_CLK    n/a            0.650         2.035       1.385      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X1Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X1Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X1Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X1Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X0Y40  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X0Y40  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X0Y41  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X0Y41  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
High Pulse Width  Slow    RFADC/FABRIC_CLK    n/a            0.650         2.034       1.384      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Fast    RFADC/FABRIC_CLK    n/a            0.650         2.034       1.384      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X1Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X1Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X1Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X1Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X0Y40  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X0Y40  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         2.034       1.492      RAMB36_X0Y41  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         2.035       1.493      RAMB36_X0Y41  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC2_CLK
  To Clock:  RFDAC2_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.034ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.377ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.034ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/FSM_sequential_time_st_reg[2]_replica/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.358ns  (logic 0.164ns (12.079%)  route 1.194ns (87.921%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.266ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.540ns = ( 5.575 - 2.035 ) 
    Source Clock Delay      (SCD):    4.147ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.436ns (routing 1.864ns, distribution 1.572ns)
  Clock Net Delay (Destination): 2.996ns (routing 1.690ns, distribution 1.306ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.436     4.147    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X79Y256        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/FSM_sequential_time_st_reg[2]_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y256        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     4.223 r  d_1_i/qick_processor_0/inst/QPROC/FSM_sequential_time_st_reg[2]_replica/Q
                         net (fo=4, routed)           0.092     4.315    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/time_st[2]_repN_alias
    SLICE_X79Y255        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.088     4.403 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/RAM_reg_i_1/O
                         net (fo=23, routed)          1.102     5.505    d_1_i/qick_processor_0/inst_n_228
    RAMB36_X6Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.996     5.575    d_1_i/qick_processor_0/t_clk_i
    RAMB36_X6Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKARDCLK
                         clock pessimism              0.341     5.916    
                         clock uncertainty           -0.035     5.881    
    RAMB36_X6Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     5.539    d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          5.539    
                         arrival time                          -5.505    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[23]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[23])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[23]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<23>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[23]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[23])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[24]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[24])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[24]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<24>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[24]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[24])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[25]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[25])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[25]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<25>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[25]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[25])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[26]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[26])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[26]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<26>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[26]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[26])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[27]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[27])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[27]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<27>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[27]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[27])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[28]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[28])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[28]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<28>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[28]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[28])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[29]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[29])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[29]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<29>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[29]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[29])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[30]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[30])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[30]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<30>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[30]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[30])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[31]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.728ns  (logic 0.946ns (54.753%)  route 0.782ns (45.247%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.567ns = ( 5.602 - 2.035 ) 
    Source Clock Delay      (SCD):    4.158ns
    Clock Pessimism Removal (CPR):    0.341ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.447ns (routing 1.864ns, distribution 1.583ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.690ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.447     4.158    d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y102      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X14Y102      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[23])
                                                      0.214     4.372 f  d_1_i/qick_processor_0/inst/QPROC/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[23]
                         net (fo=28, routed)          0.782     5.154    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[5]
    DSP48E2_X14Y87       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[5]_A_ALU[5])
                                                      0.194     5.348 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[5]
                         net (fo=1, routed)           0.000     5.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<5>
    DSP48E2_X14Y87       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[5]_ALU_OUT[31])
                                                      0.538     5.886 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[31]
                         net (fo=1, routed)           0.000     5.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<31>
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[31]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.023     5.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X14Y87       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.341     5.943    
                         clock uncertainty           -0.035     5.907    
    DSP48E2_X14Y87       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[31])
                                                      0.015     5.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.922    
                         arrival time                          -5.886    
  -------------------------------------------------------------------
                         slack                                  0.037    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[2].phase_v1_r1_reg[2][17]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[193]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.154ns  (logic 0.058ns (37.662%)  route 0.096ns (62.338%))
  Logic Levels:           0  
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.176ns
    Source Clock Delay      (SCD):    3.657ns
    Clock Pessimism Removal (CPR):    0.437ns
  Clock Net Delay (Source):      3.113ns (routing 1.690ns, distribution 1.423ns)
  Clock Net Delay (Destination): 3.465ns (routing 1.864ns, distribution 1.601ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.113     3.657    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X84Y232        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[2].phase_v1_r1_reg[2][17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y232        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.715 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[2].phase_v1_r1_reg[2][17]/Q
                         net (fo=1, routed)           0.096     3.811    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[193]
    SLICE_X85Y232        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[193]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.465     4.176    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X85Y232        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[193]/C
                         clock pessimism             -0.437     3.739    
    SLICE_X85Y232        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     3.801    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[193]
  -------------------------------------------------------------------
                         required time                         -3.801    
                         arrival time                           3.811    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.140ns (51.286%)  route 0.133ns (48.714%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.203ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.308ns
    Source Clock Delay      (SCD):    3.737ns
    Clock Pessimism Removal (CPR):    0.368ns
  Clock Net Delay (Source):      3.193ns (routing 1.690ns, distribution 1.503ns)
  Clock Net Delay (Destination): 3.597ns (routing 1.864ns, distribution 1.733ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.193     3.737    d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/aclk
    SLICE_X95Y358        FDRE                                         r  d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     3.796 r  d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[4]/Q
                         net (fo=2, routed)           0.111     3.907    d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.cos_ms1[4]
    SLICE_X95Y362        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.081     3.988 r  d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/plusOp_inferred__2/opt_has_pipe.first_q[4]_i_1/O
                         net (fo=1, routed)           0.022     4.010    d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/D[4]
    SLICE_X95Y362        FDRE                                         r  d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.597     4.308    d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/aclk
    SLICE_X95Y362        FDRE                                         r  d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/C
                         clock pessimism             -0.368     3.940    
    SLICE_X95Y362        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     4.000    d_1_i/axis_signal_gen_v6_8/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]
  -------------------------------------------------------------------
                         required time                         -4.000    
                         arrival time                           4.010    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[28].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[32].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[19][3]_srl20/D
                            (rising edge-triggered cell SRLC32E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.124ns  (logic 0.058ns (46.679%)  route 0.066ns (53.321%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.116ns
    Source Clock Delay      (SCD):    3.568ns
    Clock Pessimism Removal (CPR):    0.489ns
  Clock Net Delay (Source):      3.024ns (routing 1.690ns, distribution 1.334ns)
  Clock Net Delay (Destination): 3.405ns (routing 1.864ns, distribution 1.541ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.024     3.568    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[28].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X25Y56         FDRE                                         r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[28].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y56         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     3.626 r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[28].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[3]/Q
                         net (fo=2, routed)           0.066     3.692    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[32].i_data_casc_dly/g_parallel.g_paths[6].data_casc[29]_155[3]
    SLICE_X24Y56         SRLC32E                                      r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[32].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[19][3]_srl20/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.405     4.116    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[32].i_data_casc_dly/aclk
    SLICE_X24Y56         SRLC32E                                      r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[32].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[19][3]_srl20/CLK
                         clock pessimism             -0.489     3.627    
    SLICE_X24Y56         SRLC32E (Hold_F6LUT_SLICEM_CLK_D)
                                                      0.056     3.683    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[32].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[19][3]_srl20
  -------------------------------------------------------------------
                         required time                         -3.683    
                         arrival time                           3.692    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[42].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[41].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.213ns  (logic 0.058ns (27.187%)  route 0.155ns (72.812%))
  Logic Levels:           0  
  Clock Path Skew:        0.174ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.113ns
    Source Clock Delay      (SCD):    3.556ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Net Delay (Source):      3.012ns (routing 1.690ns, distribution 1.322ns)
  Clock Net Delay (Destination): 3.402ns (routing 1.864ns, distribution 1.538ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.012     3.556    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[42].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X31Y59         FDRE                                         r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[42].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y59         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     3.614 r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[42].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/Q
                         net (fo=2, routed)           0.155     3.769    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[41].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[1]
    SLICE_X31Y64         SRL16E                                       r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[41].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.402     4.113    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[41].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X31Y64         SRL16E                                       r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[41].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/CLK
                         clock pessimism             -0.383     3.730    
    SLICE_X31Y64         SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     3.759    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[41].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1
  -------------------------------------------------------------------
                         required time                         -3.759    
                         arrival time                           3.769    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[703]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.162ns  (logic 0.058ns (35.803%)  route 0.104ns (64.198%))
  Logic Levels:           0  
  Clock Path Skew:        0.090ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.348ns
    Source Clock Delay      (SCD):    3.804ns
    Clock Pessimism Removal (CPR):    0.454ns
  Clock Net Delay (Source):      3.260ns (routing 1.690ns, distribution 1.570ns)
  Clock Net Delay (Destination): 3.637ns (routing 1.864ns, distribution 1.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.260     3.804    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X100Y301       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y301       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.862 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]/Q
                         net (fo=1, routed)           0.104     3.966    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[703]
    SLICE_X101Y302       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[703]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.637     4.348    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X101Y302       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[703]/C
                         clock pessimism             -0.454     3.894    
    SLICE_X101Y302       FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     3.956    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[703]
  -------------------------------------------------------------------
                         required time                         -3.956    
                         arrival time                           3.966    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.058ns (27.751%)  route 0.151ns (72.249%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.073ns
    Source Clock Delay      (SCD):    3.543ns
    Clock Pessimism Removal (CPR):    0.364ns
  Clock Net Delay (Source):      2.999ns (routing 1.690ns, distribution 1.309ns)
  Clock Net Delay (Destination): 3.362ns (routing 1.864ns, distribution 1.498ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.999     3.543    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X30Y114        FDRE                                         r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y114        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     3.601 r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.151     3.752    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X30Y121        SRL16E                                       r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.362     4.073    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X30Y121        SRL16E                                       r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/CLK
                         clock pessimism             -0.364     3.709    
    SLICE_X30Y121        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     3.741    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/fir_0_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[7].g_symmetric.g_data_sym_array.g_data_sym[19].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2
  -------------------------------------------------------------------
                         required time                         -3.741    
                         arrival time                           3.752    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_register_slice_4/inst/axisc_register_slice_0/storage_data1_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.234ns  (logic 0.058ns (24.786%)  route 0.176ns (75.214%))
  Logic Levels:           0  
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.171ns
    Source Clock Delay      (SCD):    3.597ns
    Clock Pessimism Removal (CPR):    0.429ns
  Clock Net Delay (Source):      3.053ns (routing 1.690ns, distribution 1.363ns)
  Clock Net Delay (Destination): 3.460ns (routing 1.864ns, distribution 1.596ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.053     3.597    d_1_i/axis_register_slice_4/inst/axisc_register_slice_0/aclk
    SLICE_X78Y279        FDRE                                         r  d_1_i/axis_register_slice_4/inst/axisc_register_slice_0/storage_data1_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y279        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     3.655 r  d_1_i/axis_register_slice_4/inst/axisc_register_slice_0/storage_data1_reg[2]/Q
                         net (fo=1, routed)           0.176     3.831    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/DIB0
    SLICE_X76Y285        RAMD32                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.460     4.171    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X76Y285        RAMD32                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB/CLK
                         clock pessimism             -0.429     3.742    
    SLICE_X76Y285        RAMD32 (Hold_B5LUT_SLICEM_CLK_I)
                                                      0.078     3.820    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -3.820    
                         arrival time                           3.831    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[3].phase_v1_r1_reg[3][9]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[257]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.059ns (36.646%)  route 0.102ns (63.354%))
  Logic Levels:           0  
  Clock Path Skew:        0.090ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.999ns
    Source Clock Delay      (SCD):    3.487ns
    Clock Pessimism Removal (CPR):    0.421ns
  Clock Net Delay (Source):      2.943ns (routing 1.690ns, distribution 1.253ns)
  Clock Net Delay (Destination): 3.288ns (routing 1.864ns, distribution 1.424ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.943     3.487    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X52Y296        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[3].phase_v1_r1_reg[3][9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y296        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.546 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[3].phase_v1_r1_reg[3][9]/Q
                         net (fo=1, routed)           0.102     3.648    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[257]
    SLICE_X51Y296        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[257]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.288     3.999    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X51Y296        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[257]/C
                         clock pessimism             -0.421     3.578    
    SLICE_X51Y296        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     3.638    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[257]
  -------------------------------------------------------------------
                         required time                         -3.638    
                         arrival time                           3.648    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.278%)  route 0.132ns (68.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.179ns
    Source Clock Delay      (SCD):    3.618ns
    Clock Pessimism Removal (CPR):    0.440ns
  Clock Net Delay (Source):      3.074ns (routing 1.690ns, distribution 1.384ns)
  Clock Net Delay (Destination): 3.468ns (routing 1.864ns, distribution 1.604ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.074     3.618    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/aclk
    SLICE_X71Y371        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y371        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.060     3.678 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[30]/Q
                         net (fo=25, routed)          0.132     3.810    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[1]_0[0]
    SLICE_X72Y370        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.468     4.179    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X72Y370        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
                         clock pessimism             -0.440     3.739    
    SLICE_X72Y370        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     3.799    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.799    
                         arrival time                           3.810    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r1_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.123ns  (logic 0.059ns (47.968%)  route 0.064ns (52.033%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.075ns
    Source Clock Delay      (SCD):    3.546ns
    Clock Pessimism Removal (CPR):    0.480ns
  Clock Net Delay (Source):      3.002ns (routing 1.690ns, distribution 1.312ns)
  Clock Net Delay (Destination): 3.364ns (routing 1.864ns, distribution 1.500ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.002     3.546    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X62Y336        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r1_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y336        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     3.605 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r1_reg[8]/Q
                         net (fo=1, routed)           0.064     3.669    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r1[8]
    SLICE_X62Y337        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.364     4.075    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X62Y337        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[8]/C
                         clock pessimism             -0.480     3.595    
    SLICE_X62Y337        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     3.657    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.657    
                         arrival time                           3.669    
  -------------------------------------------------------------------
                         slack                                  0.011    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC2_CLK
Waveform(ns):       { 0.000 1.018 }
Period(ns):         2.035
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RFDAC/FABRIC_CLK    n/a            1.600         2.035       0.435      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     RFDAC/FABRIC_CLK    n/a            1.600         2.035       0.435      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Min Period        n/a     RFDAC/CLK_DAC       n/a            1.600         2.035       0.435      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
Min Period        n/a     RFDAC/FABRIC_CLK    n/a            1.600         2.035       0.435      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.035       0.680      RAMB36_X2Y84  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.035       0.680      RAMB36_X2Y85  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.035       0.680      RAMB36_X3Y87  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.035       0.680      RAMB36_X3Y88  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.035       0.680      RAMB36_X3Y89  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.035       0.680      RAMB36_X3Y90  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Low Pulse Width   Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RFDAC/CLK_DAC       n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
Low Pulse Width   Fast    RFDAC/CLK_DAC       n/a            0.640         1.017       0.377      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
Low Pulse Width   Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
Low Pulse Width   Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.017       0.475      RAMB36_X2Y84  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.018       0.476      RAMB36_X2Y84  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Slow    RFDAC/CLK_DAC       n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
High Pulse Width  Fast    RFDAC/CLK_DAC       n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
High Pulse Width  Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
High Pulse Width  Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.018       0.476      RAMB36_X2Y84  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.018       0.476      RAMB36_X2Y84  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        1.534ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.534ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.549ns  (logic 0.500ns (5.848%)  route 8.049ns (94.152%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns = ( 12.432 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         5.158    10.998    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X108Y170       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250    12.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y170       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[8]/C
                         clock pessimism              0.205    12.636    
                         clock uncertainty           -0.130    12.506    
    SLICE_X108Y170       FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.531    d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[8]
  -------------------------------------------------------------------
                         required time                         12.531    
                         arrival time                         -10.998    
  -------------------------------------------------------------------
                         slack                                  1.534    

Slack (MET) :             1.569ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.520ns  (logic 0.500ns (5.868%)  route 8.020ns (94.132%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.194ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.438ns = ( 12.438 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.256ns (routing 0.691ns, distribution 1.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         5.129    10.968    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X116Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.256    12.438    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X116Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[8]/C
                         clock pessimism              0.205    12.642    
                         clock uncertainty           -0.130    12.512    
    SLICE_X116Y157       FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025    12.537    d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[8]
  -------------------------------------------------------------------
                         required time                         12.537    
                         arrival time                         -10.968    
  -------------------------------------------------------------------
                         slack                                  1.569    

Slack (MET) :             1.580ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.506ns  (logic 0.500ns (5.878%)  route 8.006ns (94.122%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns = ( 12.435 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.253ns (routing 0.691ns, distribution 1.562ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         5.115    10.955    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X109Y163       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.253    12.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y163       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[8]/C
                         clock pessimism              0.205    12.639    
                         clock uncertainty           -0.130    12.509    
    SLICE_X109Y163       FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.534    d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[8]
  -------------------------------------------------------------------
                         required time                         12.534    
                         arrival time                         -10.955    
  -------------------------------------------------------------------
                         slack                                  1.580    

Slack (MET) :             1.682ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/startup_delay_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.356ns  (logic 0.500ns (5.984%)  route 7.856ns (94.017%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.387ns = ( 12.387 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.205ns (routing 0.691ns, distribution 1.514ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         4.966    10.805    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X105Y174       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/startup_delay_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.205    12.387    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y174       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/startup_delay_reg[8]/C
                         clock pessimism              0.205    12.592    
                         clock uncertainty           -0.130    12.462    
    SLICE_X105Y174       FDRE (Setup_FFF_SLICEL_C_D)
                                                      0.025    12.487    d_1_i/usp_rf_data_converter_0/inst/startup_delay_reg[8]
  -------------------------------------------------------------------
                         required time                         12.487    
                         arrival time                         -10.805    
  -------------------------------------------------------------------
                         slack                                  1.682    

Slack (MET) :             1.712ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.368ns  (logic 0.500ns (5.975%)  route 7.868ns (94.025%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.185ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns = ( 12.429 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.247ns (routing 0.691ns, distribution 1.556ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         4.977    10.816    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X110Y156       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.247    12.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y156       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[0]/C
                         clock pessimism              0.205    12.633    
                         clock uncertainty           -0.130    12.503    
    SLICE_X110Y156       FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025    12.528    d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[0]
  -------------------------------------------------------------------
                         required time                         12.528    
                         arrival time                         -10.816    
  -------------------------------------------------------------------
                         slack                                  1.712    

Slack (MET) :             1.726ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.356ns  (logic 0.500ns (5.984%)  route 7.856ns (94.016%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.187ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns = ( 12.431 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.249ns (routing 0.691ns, distribution 1.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         4.965    10.804    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X109Y160       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.249    12.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y160       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[8]/C
                         clock pessimism              0.205    12.635    
                         clock uncertainty           -0.130    12.505    
    SLICE_X109Y160       FDRE (Setup_EFF2_SLICEM_C_D)
                                                      0.025    12.530    d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[8]
  -------------------------------------------------------------------
                         required time                         12.530    
                         arrival time                         -10.804    
  -------------------------------------------------------------------
                         slack                                  1.726    

Slack (MET) :             1.728ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.356ns  (logic 0.416ns (4.979%)  route 7.940ns (95.021%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns = ( 12.432 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.138     3.232    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X61Y158        LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     3.330 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.302     5.632    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X31Y93         LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     5.669 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[14]_INST_0/O
                         net (fo=179, routed)         5.135    10.804    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[14]
    SLICE_X111Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250    12.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[14]/C
                         clock pessimism              0.205    12.637    
                         clock uncertainty           -0.130    12.507    
    SLICE_X111Y157       FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.025    12.532    d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[14]
  -------------------------------------------------------------------
                         required time                         12.532    
                         arrival time                         -10.804    
  -------------------------------------------------------------------
                         slack                                  1.728    

Slack (MET) :             1.804ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.282ns  (logic 0.416ns (5.023%)  route 7.866ns (94.977%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns = ( 12.435 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.253ns (routing 0.691ns, distribution 1.562ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.138     3.232    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X61Y158        LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     3.330 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.302     5.632    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X31Y93         LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     5.669 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[14]_INST_0/O
                         net (fo=179, routed)         5.062    10.730    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[14]
    SLICE_X109Y163       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.253    12.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y163       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[14]/C
                         clock pessimism              0.205    12.639    
                         clock uncertainty           -0.130    12.509    
    SLICE_X109Y163       FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.025    12.534    d_1_i/usp_rf_data_converter_0/inst/adc2_clk_detect_reg[14]
  -------------------------------------------------------------------
                         required time                         12.534    
                         arrival time                         -10.730    
  -------------------------------------------------------------------
                         slack                                  1.804    

Slack (MET) :             1.818ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.269ns  (logic 0.500ns (6.047%)  route 7.769ns (93.953%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns = ( 12.436 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.254ns (routing 0.691ns, distribution 1.563ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         4.878    10.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X109Y166       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.254    12.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y166       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[8]/C
                         clock pessimism              0.205    12.640    
                         clock uncertainty           -0.130    12.510    
    SLICE_X109Y166       FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    12.535    d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[8]
  -------------------------------------------------------------------
                         required time                         12.535    
                         arrival time                         -10.717    
  -------------------------------------------------------------------
                         slack                                  1.818    

Slack (MET) :             1.950ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_calibration_timer_i_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.079ns  (logic 0.500ns (6.189%)  route 7.579ns (93.811%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        0.134ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.378ns = ( 12.378 - 10.000 ) 
    Source Clock Delay      (SCD):    2.448ns
    Clock Pessimism Removal (CPR):    0.205ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.222ns (routing 0.764ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.196ns (routing 0.691ns, distribution 1.505ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.448    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X62Y157        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y157        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.529 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.196     2.725    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X62Y157        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     2.775 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.169     2.944    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X62Y159        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     3.094 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.184     3.278    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X62Y159        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.374 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2/O
                         net (fo=36, routed)          2.342     5.716    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_2_n_0
    SLICE_X27Y87         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     5.839 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[8]_INST_0/O
                         net (fo=155, routed)         4.689    10.528    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[8]
    SLICE_X98Y171        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_calibration_timer_i_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.196    12.378    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X98Y171        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_calibration_timer_i_reg[8]/C
                         clock pessimism              0.205    12.582    
                         clock uncertainty           -0.130    12.452    
    SLICE_X98Y171        FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.477    d_1_i/usp_rf_data_converter_0/inst/adc0_calibration_timer_i_reg[8]
  -------------------------------------------------------------------
                         required time                         12.477    
                         arrival time                         -10.528    
  -------------------------------------------------------------------
                         slack                                  1.950    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/m_vector_i_reg[1068]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/skid_buffer_reg[1068]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.174ns  (logic 0.058ns (33.306%)  route 0.116ns (66.694%))
  Logic Levels:           0  
  Clock Path Skew:        0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.485ns
    Source Clock Delay      (SCD):    2.178ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.996ns (routing 0.691ns, distribution 1.305ns)
  Clock Net Delay (Destination): 2.259ns (routing 0.764ns, distribution 1.495ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.996     2.178    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/aclk
    SLICE_X23Y209        FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/m_vector_i_reg[1068]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X23Y209        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     2.236 r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_sreg/m_vector_i_reg[1068]/Q
                         net (fo=2, routed)           0.116     2.352    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/skid_buffer_reg[1144]_0[10]
    SLICE_X22Y208        FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/skid_buffer_reg[1068]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.259     2.485    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/aclk
    SLICE_X22Y208        FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/skid_buffer_reg[1068]/C
                         clock pessimism             -0.203     2.282    
    SLICE_X22Y208        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     2.342    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/aw_reg_stall/skid_buffer_reg[1068]
  -------------------------------------------------------------------
                         required time                         -2.342    
                         arrival time                           2.352    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_A5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA_D1/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_A6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_B5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB_D1/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_B6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_C5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC_D1/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_C6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMC_D1
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_D5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD_D1/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_D6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAMD_D1
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAME/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.058ns (25.688%)  route 0.168ns (74.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    2.174ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.992ns (routing 0.691ns, distribution 1.301ns)
  Clock Net Delay (Destination): 2.279ns (routing 0.764ns, distribution 1.515ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.992     2.174    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/wr_clk
    SLICE_X26Y217        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y217        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.232 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/Q
                         net (fo=26, routed)          0.168     2.400    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/ADDRH1
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAME/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.279     2.505    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/WCLK
    SLICE_X27Y214        RAMD32                                       r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAME/CLK
                         clock pessimism             -0.203     2.301    
    SLICE_X27Y214        RAMD32 (Hold_E5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.389    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_9/RAME
  -------------------------------------------------------------------
                         required time                         -2.389    
                         arrival time                           2.400    
  -------------------------------------------------------------------
                         slack                                  0.010    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location    Pin
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     RFDAC/DCLK         n/a            4.000         10.000      6.000      RFDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Min Period        n/a     RFDAC/DCLK         n/a            4.000         10.000      6.000      RFDAC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DCLK
Min Period        n/a     RFDAC/DCLK         n/a            4.000         10.000      6.000      RFDAC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/DCLK
Min Period        n/a     RFDAC/DCLK         n/a            4.000         10.000      6.000      RFDAC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/DCLK
Min Period        n/a     PS8/MAXIGP0ACLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
Min Period        n/a     PS8/SAXIGP0RCLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0RCLK
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCM_X0Y7   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y7   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y7   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y7   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y7   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Slow    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Fast    RFADC/DCLK         n/a            1.600         5.000       3.400      RFADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.336ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.019ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.958ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.336ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[25]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.167ns  (logic 0.079ns (1.896%)  route 4.088ns (98.104%))
  Logic Levels:           0  
  Clock Path Skew:        -0.159ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.366ns = ( 10.366 - 5.000 ) 
    Source Clock Delay      (SCD):    5.216ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.595ns (routing 1.545ns, distribution 1.050ns)
  Clock Net Delay (Destination): 2.291ns (routing 1.400ns, distribution 0.891ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.595     5.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X65Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.295 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/Q
                         net (fo=26, routed)          4.088     9.383    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/fifo_mem/data_i[25]
    RAMB36_X7Y43         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.291    10.366    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X7Y43         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism             -0.309    10.057    
                         clock uncertainty           -0.062     9.995    
    RAMB36_X7Y43         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[25])
                                                     -0.276     9.719    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                          9.719    
                         arrival time                          -9.383    
  -------------------------------------------------------------------
                         slack                                  0.336    

Slack (MET) :             0.382ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/DINADIN[25]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.119ns  (logic 0.079ns (1.918%)  route 4.040ns (98.082%))
  Logic Levels:           0  
  Clock Path Skew:        -0.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.364ns = ( 10.364 - 5.000 ) 
    Source Clock Delay      (SCD):    5.216ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.595ns (routing 1.545ns, distribution 1.050ns)
  Clock Net Delay (Destination): 2.289ns (routing 1.400ns, distribution 0.889ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.595     5.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X65Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.295 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/Q
                         net (fo=26, routed)          4.040     9.335    d_1_i/qick_processor_0/QPROC/DISPATCHER/c_fifo_time_in_r[25]
    RAMB36_X6Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/DINADIN[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.289    10.364    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X6Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.309    10.055    
                         clock uncertainty           -0.062     9.993    
    RAMB36_X6Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[25])
                                                     -0.276     9.717    d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.717    
                         arrival time                          -9.335    
  -------------------------------------------------------------------
                         slack                                  0.382    

Slack (MET) :             0.453ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[25]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.048ns  (logic 0.079ns (1.952%)  route 3.969ns (98.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.364ns = ( 10.364 - 5.000 ) 
    Source Clock Delay      (SCD):    5.216ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.595ns (routing 1.545ns, distribution 1.050ns)
  Clock Net Delay (Destination): 2.289ns (routing 1.400ns, distribution 0.889ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.595     5.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X65Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.295 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/Q
                         net (fo=26, routed)          3.969     9.264    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/data_i[25]
    RAMB36_X7Y41         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.289    10.364    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X7Y41         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism             -0.309    10.055    
                         clock uncertainty           -0.062     9.993    
    RAMB36_X7Y41         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[25])
                                                     -0.276     9.717    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                          9.717    
                         arrival time                          -9.264    
  -------------------------------------------------------------------
                         slack                                  0.453    

Slack (MET) :             0.499ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/DINADIN[25]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.010ns  (logic 0.079ns (1.970%)  route 3.931ns (98.030%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.372ns = ( 10.372 - 5.000 ) 
    Source Clock Delay      (SCD):    5.216ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.595ns (routing 1.545ns, distribution 1.050ns)
  Clock Net Delay (Destination): 2.297ns (routing 1.400ns, distribution 0.897ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.595     5.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X65Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.295 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/Q
                         net (fo=26, routed)          3.931     9.226    d_1_i/qick_processor_0/QPROC/DISPATCHER/c_fifo_time_in_r[25]
    RAMB36_X7Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/DINADIN[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.297    10.372    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X7Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.309    10.063    
                         clock uncertainty           -0.062    10.001    
    RAMB36_X7Y44         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[25])
                                                     -0.276     9.725    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.725    
                         arrival time                          -9.226    
  -------------------------------------------------------------------
                         slack                                  0.499    

Slack (MET) :             0.561ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.680ns  (logic 0.564ns (15.325%)  route 3.116ns (84.675%))
  Logic Levels:           6  (LUT4=1 LUT5=4 LUT6=1)
  Clock Path Skew:        -0.303ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.376ns = ( 10.376 - 5.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.749ns (routing 1.545ns, distribution 1.204ns)
  Clock Net Delay (Destination): 2.301ns (routing 1.400ns, distribution 0.901ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.749     5.370    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y265        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.451 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/Q
                         net (fo=1, routed)           0.193     5.644    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/out[6]
    SLICE_X91Y265        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.790 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15/O
                         net (fo=3, routed)           0.204     5.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15_n_0
    SLICE_X89Y264        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     6.031 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_32/O
                         net (fo=2, routed)           0.848     6.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][14]_i_15[0]
    SLICE_X78Y250        LUT4 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     7.004 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_15/O
                         net (fo=3, routed)           0.290     7.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg_0
    SLICE_X74Y248        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     7.384 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=3, routed)           0.156     7.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X74Y249        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     7.575 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=593, routed)         0.740     8.315    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_0
    SLICE_X68Y217        LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     8.365 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__7/O
                         net (fo=24, routed)          0.685     9.050    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/do_push
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.301    10.376    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
                         clock pessimism             -0.309    10.067    
                         clock uncertainty           -0.062    10.005    
    RAMB36_X7Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[6])
                                                     -0.394     9.611    d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1
  -------------------------------------------------------------------
                         required time                          9.611    
                         arrival time                          -9.050    
  -------------------------------------------------------------------
                         slack                                  0.561    

Slack (MET) :             0.565ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[5]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.676ns  (logic 0.564ns (15.341%)  route 3.112ns (84.659%))
  Logic Levels:           6  (LUT4=1 LUT5=4 LUT6=1)
  Clock Path Skew:        -0.303ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.376ns = ( 10.376 - 5.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.749ns (routing 1.545ns, distribution 1.204ns)
  Clock Net Delay (Destination): 2.301ns (routing 1.400ns, distribution 0.901ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.749     5.370    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y265        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.451 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/Q
                         net (fo=1, routed)           0.193     5.644    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/out[6]
    SLICE_X91Y265        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.790 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15/O
                         net (fo=3, routed)           0.204     5.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15_n_0
    SLICE_X89Y264        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     6.031 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_32/O
                         net (fo=2, routed)           0.848     6.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][14]_i_15[0]
    SLICE_X78Y250        LUT4 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     7.004 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_15/O
                         net (fo=3, routed)           0.290     7.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg_0
    SLICE_X74Y248        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     7.384 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=3, routed)           0.156     7.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X74Y249        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     7.575 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=593, routed)         0.740     8.315    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_0
    SLICE_X68Y217        LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     8.365 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__7/O
                         net (fo=24, routed)          0.681     9.046    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/do_push
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[5]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.301    10.376    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
                         clock pessimism             -0.309    10.067    
                         clock uncertainty           -0.062    10.005    
    RAMB36_X7Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[5])
                                                     -0.394     9.611    d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1
  -------------------------------------------------------------------
                         required time                          9.611    
                         arrival time                          -9.046    
  -------------------------------------------------------------------
                         slack                                  0.565    

Slack (MET) :             0.571ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[4]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.670ns  (logic 0.564ns (15.366%)  route 3.106ns (84.634%))
  Logic Levels:           6  (LUT4=1 LUT5=4 LUT6=1)
  Clock Path Skew:        -0.303ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.376ns = ( 10.376 - 5.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.749ns (routing 1.545ns, distribution 1.204ns)
  Clock Net Delay (Destination): 2.301ns (routing 1.400ns, distribution 0.901ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.749     5.370    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y265        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.451 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/Q
                         net (fo=1, routed)           0.193     5.644    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/out[6]
    SLICE_X91Y265        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.790 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15/O
                         net (fo=3, routed)           0.204     5.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15_n_0
    SLICE_X89Y264        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     6.031 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_32/O
                         net (fo=2, routed)           0.848     6.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][14]_i_15[0]
    SLICE_X78Y250        LUT4 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     7.004 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_15/O
                         net (fo=3, routed)           0.290     7.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg_0
    SLICE_X74Y248        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     7.384 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=3, routed)           0.156     7.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X74Y249        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     7.575 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=593, routed)         0.740     8.315    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_0
    SLICE_X68Y217        LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     8.365 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__7/O
                         net (fo=24, routed)          0.675     9.040    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/do_push
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[4]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.301    10.376    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
                         clock pessimism             -0.309    10.067    
                         clock uncertainty           -0.062    10.005    
    RAMB36_X7Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[4])
                                                     -0.394     9.611    d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1
  -------------------------------------------------------------------
                         required time                          9.611    
                         arrival time                          -9.040    
  -------------------------------------------------------------------
                         slack                                  0.571    

Slack (MET) :             0.574ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.667ns  (logic 0.564ns (15.379%)  route 3.103ns (84.621%))
  Logic Levels:           6  (LUT4=1 LUT5=4 LUT6=1)
  Clock Path Skew:        -0.303ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.376ns = ( 10.376 - 5.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.749ns (routing 1.545ns, distribution 1.204ns)
  Clock Net Delay (Destination): 2.301ns (routing 1.400ns, distribution 0.901ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.749     5.370    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y265        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.451 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/Q
                         net (fo=1, routed)           0.193     5.644    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/out[6]
    SLICE_X91Y265        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.790 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15/O
                         net (fo=3, routed)           0.204     5.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15_n_0
    SLICE_X89Y264        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     6.031 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_32/O
                         net (fo=2, routed)           0.848     6.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][14]_i_15[0]
    SLICE_X78Y250        LUT4 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     7.004 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_15/O
                         net (fo=3, routed)           0.290     7.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg_0
    SLICE_X74Y248        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     7.384 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=3, routed)           0.156     7.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X74Y249        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     7.575 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=593, routed)         0.740     8.315    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_0
    SLICE_X68Y217        LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     8.365 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__7/O
                         net (fo=24, routed)          0.672     9.037    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/do_push
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.301    10.376    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
                         clock pessimism             -0.309    10.067    
                         clock uncertainty           -0.062    10.005    
    RAMB36_X7Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[7])
                                                     -0.394     9.611    d_1_i/qick_processor_0/WAVE_FIFO[9].wave_fifo_inst/fifo_mem/RAM_reg_1
  -------------------------------------------------------------------
                         required time                          9.611    
                         arrival time                          -9.037    
  -------------------------------------------------------------------
                         slack                                  0.574    

Slack (MET) :             0.577ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_alu_src]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/DINBDIN[4]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.008ns  (logic 0.774ns (19.313%)  route 3.234ns (80.687%))
  Logic Levels:           8  (LUT3=2 LUT5=3 LUT6=2 MUXF7=1)
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.422ns = ( 10.422 - 5.000 ) 
    Source Clock Delay      (SCD):    5.218ns
    Clock Pessimism Removal (CPR):    -0.301ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.597ns (routing 1.545ns, distribution 1.052ns)
  Clock Net Delay (Destination): 2.347ns (routing 1.400ns, distribution 0.947ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.597     5.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X75Y246        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_alu_src]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y246        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.294 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_alu_src]/Q
                         net (fo=233, routed)         0.578     5.872    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_ctrl_reg[cfg_alu_src]
    SLICE_X69Y240        LUT3 (Prop_H5LUT_SLICEM_I2_O)
                                                      0.066     5.938 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[31]_i_14/O
                         net (fo=90, routed)          0.422     6.360    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_alu_in_B[2]
    SLICE_X78Y237        LUT5 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.097     6.457 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[23]_i_14/O
                         net (fo=2, routed)           0.374     6.831    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[23]_i_14_n_0
    SLICE_X77Y244        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.089     6.920 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[23]_i_13/O
                         net (fo=2, routed)           0.223     7.143    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[23]_i_13_n_0
    SLICE_X74Y245        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     7.231 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[22]_i_12/O
                         net (fo=1, routed)           0.188     7.419    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/alu/r_x1_alu_dt_reg[22]_i_4_0
    SLICE_X73Y245        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.049     7.468 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/alu/r_x1_alu_dt[22]_i_8/O
                         net (fo=1, routed)           0.011     7.479    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/alu/r_x1_alu_dt[22]_i_8_n_0
    SLICE_X73Y245        MUXF7 (Prop_F7MUX_EF_SLICEL_I0_O)
                                                      0.064     7.543 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/alu/r_x1_alu_dt_reg[22]_i_4/O
                         net (fo=1, routed)           0.225     7.768    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt_reg[22]
    SLICE_X74Y245        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.123     7.891 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/r_x1_alu_dt[22]_i_1/O
                         net (fo=7, routed)           0.260     8.151    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/x1_alu_dt[22]
    SLICE_X73Y248        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.122     8.273 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_8_i_7/O
                         net (fo=4, routed)           0.953     9.226    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/dmem_w_dt[22]
    RAMB36_X7Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/DINBDIN[4]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.347    10.422    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
                         clock pessimism             -0.301    10.121    
                         clock uncertainty           -0.062    10.059    
    RAMB36_X7Y67         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[4])
                                                     -0.256     9.803    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11
  -------------------------------------------------------------------
                         required time                          9.803    
                         arrival time                          -9.226    
  -------------------------------------------------------------------
                         slack                                  0.577    

Slack (MET) :             0.578ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[25]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.911ns  (logic 0.079ns (2.020%)  route 3.832ns (97.980%))
  Logic Levels:           0  
  Clock Path Skew:        -0.173ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.352ns = ( 10.352 - 5.000 ) 
    Source Clock Delay      (SCD):    5.216ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.595ns (routing 1.545ns, distribution 1.050ns)
  Clock Net Delay (Destination): 2.277ns (routing 1.400ns, distribution 0.877ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.595     5.216    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X65Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.295 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[25]/Q
                         net (fo=26, routed)          3.832     9.127    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/data_i[25]
    RAMB36_X6Y41         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.277    10.352    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X6Y41         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism             -0.309    10.043    
                         clock uncertainty           -0.062     9.981    
    RAMB36_X6Y41         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[25])
                                                     -0.276     9.705    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                          9.705    
                         arrival time                          -9.127    
  -------------------------------------------------------------------
                         slack                                  0.578    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.264ns  (logic 0.125ns (47.355%)  route 0.139ns (52.645%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.185ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.239ns
    Source Clock Delay      (SCD):    5.363ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Net Delay (Source):      2.288ns (routing 1.400ns, distribution 0.888ns)
  Clock Net Delay (Destination): 2.618ns (routing 1.545ns, distribution 1.073ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.288     5.363    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X78Y238        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y238        FDPE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.422 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/Q
                         net (fo=8, routed)           0.110     5.532    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[0]
    SLICE_X78Y242        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.066     5.598 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[3]_i_1__1/O
                         net (fo=1, routed)           0.029     5.627    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/p_0_in__0[3]
    SLICE_X78Y242        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.618     5.239    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X78Y242        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/C
                         clock pessimism              0.309     5.548    
    SLICE_X78Y242        FDCE (Hold_BFF_SLICEM_C_D)
                                                      0.060     5.608    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -5.608    
                         arrival time                           5.627    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][17]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.174ns  (logic 0.094ns (54.023%)  route 0.080ns (45.977%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.288ns
    Source Clock Delay      (SCD):    5.446ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Net Delay (Source):      2.371ns (routing 1.400ns, distribution 0.971ns)
  Clock Net Delay (Destination): 2.667ns (routing 1.545ns, distribution 1.122ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.371     5.446    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X55Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y278        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     5.505 r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][17]/Q
                         net (fo=1, routed)           0.058     5.563    d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[63]_2[17]
    SLICE_X57Y278        LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.035     5.598 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r[17]_i_1/O
                         net (fo=1, routed)           0.022     5.620    d_1_i/qick_processor_0/inst/QPROC/CORE_0/p_0_in_0[17]
    SLICE_X57Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.667     5.288    d_1_i/qick_processor_0/inst/QPROC/CORE_0/c_clk_i
    SLICE_X57Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[17]/C
                         clock pessimism              0.250     5.538    
    SLICE_X57Y278        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     5.598    d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[17]
  -------------------------------------------------------------------
                         required time                         -5.598    
                         arrival time                           5.620    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.126ns  (logic 0.058ns (46.032%)  route 0.068ns (53.968%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.282ns
    Source Clock Delay      (SCD):    5.444ns
    Clock Pessimism Removal (CPR):    -0.202ns
  Clock Net Delay (Source):      2.369ns (routing 1.400ns, distribution 0.969ns)
  Clock Net Delay (Destination): 2.661ns (routing 1.545ns, distribution 1.116ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.369     5.444    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y277        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y277        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.502 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16]/Q
                         net (fo=1, routed)           0.068     5.570    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s1_axis_tdata[16]
    SLICE_X55Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.661     5.282    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X55Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][16]/C
                         clock pessimism              0.202     5.484    
    SLICE_X55Y278        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     5.546    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][16]
  -------------------------------------------------------------------
                         required time                         -5.546    
                         arrival time                           5.570    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.058ns (42.647%)  route 0.078ns (57.353%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.265ns
    Source Clock Delay      (SCD):    5.421ns
    Clock Pessimism Removal (CPR):    -0.207ns
  Clock Net Delay (Source):      2.346ns (routing 1.400ns, distribution 0.946ns)
  Clock Net Delay (Destination): 2.644ns (routing 1.545ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.346     5.421    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y234        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y234        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.479 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][16]/Q
                         net (fo=1, routed)           0.078     5.557    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s0_axis_tdata[16]
    SLICE_X55Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.644     5.265    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X55Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][16]/C
                         clock pessimism              0.207     5.472    
    SLICE_X55Y235        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     5.532    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][16]
  -------------------------------------------------------------------
                         required time                         -5.532    
                         arrival time                           5.557    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.095ns (50.800%)  route 0.092ns (49.200%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.189ns
    Source Clock Delay      (SCD):    5.347ns
    Clock Pessimism Removal (CPR):    -0.260ns
  Clock Net Delay (Source):      2.272ns (routing 1.400ns, distribution 0.872ns)
  Clock Net Delay (Destination): 2.568ns (routing 1.545ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.272     5.347    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y233        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     5.407 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.066     5.473    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/clear_r
    SLICE_X72Y233        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.035     5.508 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_r[1]_i_1__9/O
                         net (fo=1, routed)           0.026     5.534    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/p_0_in__0[1]
    SLICE_X72Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.568     5.189    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X72Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                         clock pessimism              0.260     5.449    
    SLICE_X72Y233        FDCE (Hold_EFF_SLICEM_C_D)
                                                      0.060     5.509    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.509    
                         arrival time                           5.534    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.082ns (48.030%)  route 0.089ns (51.970%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.162ns
    Source Clock Delay      (SCD):    5.336ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Net Delay (Source):      2.261ns (routing 1.400ns, distribution 0.861ns)
  Clock Net Delay (Destination): 2.541ns (routing 1.545ns, distribution 0.996ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.261     5.336    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y231        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     5.396 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.065     5.461    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/clear_r
    SLICE_X71Y231        LUT2 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.022     5.483 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[7]_i_1__7/O
                         net (fo=1, routed)           0.024     5.507    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[7]_i_1__7_n_0
    SLICE_X71Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.541     5.162    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                         clock pessimism              0.259     5.421    
    SLICE_X71Y231        FDCE (Hold_FFF_SLICEL_C_D)
                                                      0.060     5.481    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                         -5.481    
                         arrival time                           5.507    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.282ns
    Source Clock Delay      (SCD):    5.443ns
    Clock Pessimism Removal (CPR):    -0.202ns
  Clock Net Delay (Source):      2.368ns (routing 1.400ns, distribution 0.968ns)
  Clock Net Delay (Destination): 2.661ns (routing 1.545ns, distribution 1.116ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.368     5.443    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y279        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y279        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.501 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][1]/Q
                         net (fo=1, routed)           0.072     5.573    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s1_axis_tdata[1]
    SLICE_X55Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.661     5.282    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X55Y278        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][1]/C
                         clock pessimism              0.202     5.484    
    SLICE_X55Y278        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     5.546    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][1]
  -------------------------------------------------------------------
                         required time                         -5.546    
                         arrival time                           5.573    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][42]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.058ns (41.429%)  route 0.082ns (58.571%))
  Logic Levels:           0  
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.266ns
    Source Clock Delay      (SCD):    5.421ns
    Clock Pessimism Removal (CPR):    -0.207ns
  Clock Net Delay (Source):      2.346ns (routing 1.400ns, distribution 0.946ns)
  Clock Net Delay (Destination): 2.645ns (routing 1.545ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.346     5.421    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y235        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y235        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.479 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]/Q
                         net (fo=1, routed)           0.082     5.561    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]
    SLICE_X55Y237        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][42]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.645     5.266    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y237        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][42]/C
                         clock pessimism              0.207     5.473    
    SLICE_X55Y237        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.060     5.533    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][42]
  -------------------------------------------------------------------
                         required time                         -5.533    
                         arrival time                           5.561    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][37]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][37]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.271ns  (logic 0.060ns (22.140%)  route 0.211ns (77.860%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.299ns
    Source Clock Delay      (SCD):    5.425ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Net Delay (Source):      2.350ns (routing 1.400ns, distribution 0.950ns)
  Clock Net Delay (Destination): 2.678ns (routing 1.545ns, distribution 1.133ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.350     5.425    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y236        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][37]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y236        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     5.485 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][37]/Q
                         net (fo=1, routed)           0.211     5.696    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s0_axis_tdata[37]
    SLICE_X56Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][37]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.678     5.299    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X56Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][37]/C
                         clock pessimism              0.309     5.608    
    SLICE_X56Y240        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     5.668    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[0].port_dt_r_reg[0][37]
  -------------------------------------------------------------------
                         required time                         -5.668    
                         arrival time                           5.696    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.039ns (48.148%)  route 0.042ns (51.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.027ns
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    -0.150ns
  Clock Net Delay (Source):      1.423ns (routing 0.846ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.605ns (routing 0.950ns, distribution 0.655ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.423     3.172    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/CLK
    SLICE_X66Y250        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y250        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     3.211 r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_has_c.i_c3/opt_has_pipe.first_q_reg[3]/Q
                         net (fo=1, routed)           0.042     3.253    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[3]_0
    SLICE_X66Y250        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.605     3.027    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/CLK
    SLICE_X66Y250        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[3]/C
                         clock pessimism              0.150     3.178    
    SLICE_X66Y250        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     3.225    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/ARITH_DSP/U0/i_synth/i_synth_option.i_synth_model/i_c4/opt_has_pipe.first_q_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.225    
                         arrival time                           3.253    
  -------------------------------------------------------------------
                         slack                                  0.028    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_core_0
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y48  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y49  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y66  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y67  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y31  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y32  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB18_X6Y72  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_14/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y50  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y51  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y52  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y52  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y52  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y51  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y51  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y46  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y46  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y52  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y52  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y51  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y51  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y46  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y46  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       12.699ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.028ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       24.468ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             12.699ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.962ns  (logic 0.299ns (15.237%)  route 1.663ns (84.763%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -10.103ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 25.000 - 25.000 ) 
    Source Clock Delay      (SCD):    10.103ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      2.690ns (routing 1.824ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.690    10.103    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y29        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y29        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[2]/Q
                         net (fo=50, routed)          0.414    10.596    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[2]
    SLICE_X101Y26        LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.150    10.746 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_bscanid_en_INST_0/O
                         net (fo=35, routed)          0.051    10.797    dbg_hub/inst/BSCANID.u_xsdbm_id/bscanid_en_int
    SLICE_X101Y26        LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.035    10.832 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch_i_1/O
                         net (fo=2, routed)           0.286    11.118    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_tdo[0]
    SLICE_X102Y29        LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.035    11.153 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdo_INST_0/O
                         net (fo=1, routed)           0.912    12.065    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TDO
    CONFIG_SITE_X0Y0     BSCANE2                                      r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                         clock pessimism              0.000    25.000    
                         clock uncertainty           -0.235    24.765    
    CONFIG_SITE_X0Y0     BSCANE2 (Setup_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TDO)
                                                      0.000    24.765    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
  -------------------------------------------------------------------
                         required time                         24.765    
                         arrival time                         -12.065    
  -------------------------------------------------------------------
                         slack                                 12.699    

Slack (MET) :             21.861ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.500ns  (logic 5.320ns (81.847%)  route 1.180ns (18.153%))
  Logic Levels:           3  (LUT3=1 LUT6=2)
  Clock Path Skew:        3.574ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.574ns = ( 53.574 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.481ns (routing 0.999ns, distribution 0.482ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=4, routed)           0.959    31.059    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_update
    SLICE_X99Y27         LUT3 (Prop_A5LUT_SLICEM_I2_O)
                                                      0.068    31.127 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_3/O
                         net (fo=3, routed)           0.138    31.265    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_3_n_0
    SLICE_X100Y29        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.076    31.341 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[1]_i_2/O
                         net (fo=1, routed)           0.036    31.377    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[1]_i_2_n_0
    SLICE_X100Y29        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.076    31.453 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[1]_i_1/O
                         net (fo=1, routed)           0.047    31.500    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[1]_i_1_n_0
    SLICE_X100Y29        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.481    53.574    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y29        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[1]/C
                         clock pessimism              0.000    53.574    
                         clock uncertainty           -0.235    53.338    
    SLICE_X100Y29        FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.023    53.361    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[1]
  -------------------------------------------------------------------
                         required time                         53.361    
                         arrival time                         -31.500    
  -------------------------------------------------------------------
                         slack                                 21.861    

Slack (MET) :             21.875ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.429ns  (logic 5.133ns (79.843%)  route 1.296ns (20.157%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.584ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.584ns = ( 53.584 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.491ns (routing 0.999ns, distribution 0.492ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          0.971    31.071    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X98Y25         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.033    31.104 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.325    31.429    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X99Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.491    53.584    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X99Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[1]/C
                         clock pessimism              0.000    53.584    
                         clock uncertainty           -0.235    53.348    
    SLICE_X99Y28         FDRE (Setup_DFF_SLICEM_C_R)
                                                     -0.044    53.304    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[1]
  -------------------------------------------------------------------
                         required time                         53.304    
                         arrival time                         -31.429    
  -------------------------------------------------------------------
                         slack                                 21.875    

Slack (MET) :             21.875ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.429ns  (logic 5.133ns (79.843%)  route 1.296ns (20.157%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.584ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.584ns = ( 53.584 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.491ns (routing 0.999ns, distribution 0.492ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          0.971    31.071    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X98Y25         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.033    31.104 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.325    31.429    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X99Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.491    53.584    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X99Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[2]/C
                         clock pessimism              0.000    53.584    
                         clock uncertainty           -0.235    53.348    
    SLICE_X99Y28         FDRE (Setup_CFF_SLICEM_C_R)
                                                     -0.044    53.304    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[2]
  -------------------------------------------------------------------
                         required time                         53.304    
                         arrival time                         -31.429    
  -------------------------------------------------------------------
                         slack                                 21.875    

Slack (MET) :             21.875ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.429ns  (logic 5.133ns (79.843%)  route 1.296ns (20.157%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.584ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.584ns = ( 53.584 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.491ns (routing 0.999ns, distribution 0.492ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          0.971    31.071    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X98Y25         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.033    31.104 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.325    31.429    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X99Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.491    53.584    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X99Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[4]/C
                         clock pessimism              0.000    53.584    
                         clock uncertainty           -0.235    53.348    
    SLICE_X99Y28         FDRE (Setup_BFF_SLICEM_C_R)
                                                     -0.044    53.304    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[4]
  -------------------------------------------------------------------
                         required time                         53.304    
                         arrival time                         -31.429    
  -------------------------------------------------------------------
                         slack                                 21.875    

Slack (MET) :             21.881ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.420ns  (logic 5.133ns (79.955%)  route 1.287ns (20.045%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.581ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.581ns = ( 53.581 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.488ns (routing 0.999ns, distribution 0.489ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          0.971    31.071    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X98Y25         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.033    31.104 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.316    31.420    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X100Y28        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.488    53.581    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y28        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[0]/C
                         clock pessimism              0.000    53.581    
                         clock uncertainty           -0.235    53.345    
    SLICE_X100Y28        FDRE (Setup_BFF2_SLICEL_C_R)
                                                     -0.044    53.301    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[0]
  -------------------------------------------------------------------
                         required time                         53.301    
                         arrival time                         -31.420    
  -------------------------------------------------------------------
                         slack                                 21.881    

Slack (MET) :             21.881ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.420ns  (logic 5.133ns (79.955%)  route 1.287ns (20.045%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.581ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.581ns = ( 53.581 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.488ns (routing 0.999ns, distribution 0.489ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          0.971    31.071    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X98Y25         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.033    31.104 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.316    31.420    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X100Y28        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.488    53.581    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y28        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[5]/C
                         clock pessimism              0.000    53.581    
                         clock uncertainty           -0.235    53.345    
    SLICE_X100Y28        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.044    53.301    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[5]
  -------------------------------------------------------------------
                         required time                         53.301    
                         arrival time                         -31.420    
  -------------------------------------------------------------------
                         slack                                 21.881    

Slack (MET) :             21.881ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.420ns  (logic 5.133ns (79.955%)  route 1.287ns (20.045%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.581ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.581ns = ( 53.581 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.488ns (routing 0.999ns, distribution 0.489ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          0.971    31.071    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X98Y25         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.033    31.104 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.316    31.420    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X100Y28        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.488    53.581    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y28        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]/C
                         clock pessimism              0.000    53.581    
                         clock uncertainty           -0.235    53.345    
    SLICE_X100Y28        FDRE (Setup_CFF_SLICEL_C_R)
                                                     -0.044    53.301    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]
  -------------------------------------------------------------------
                         required time                         53.301    
                         arrival time                         -31.420    
  -------------------------------------------------------------------
                         slack                                 21.881    

Slack (MET) :             21.900ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.461ns  (logic 5.302ns (82.057%)  route 1.159ns (17.943%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        3.574ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.574ns = ( 53.574 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.481ns (routing 0.999ns, distribution 0.482ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SEL)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SEL
                         net (fo=8, routed)           0.909    31.009    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_sel
    SLICE_X100Y29        LUT5 (Prop_A5LUT_SLICEL_I4_O)
                                                      0.109    31.118 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_4/O
                         net (fo=2, routed)           0.204    31.322    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_4_n_0
    SLICE_X100Y29        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.093    31.415 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_1/O
                         net (fo=1, routed)           0.046    31.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_1_n_0
    SLICE_X100Y29        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.481    53.574    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y29        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]/C
                         clock pessimism              0.000    53.574    
                         clock uncertainty           -0.235    53.338    
    SLICE_X100Y29        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.023    53.361    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]
  -------------------------------------------------------------------
                         required time                         53.361    
                         arrival time                         -31.461    
  -------------------------------------------------------------------
                         slack                                 21.900    

Slack (MET) :             21.906ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.400ns  (logic 5.280ns (82.505%)  route 1.120ns (17.495%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.585ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.585ns = ( 53.585 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.492ns (routing 0.999ns, distribution 0.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.678    30.778    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X98Y25         LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.076    30.854 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           0.197    31.051    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X99Y19         LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.052    31.103 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    31.165    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X99Y19         LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    31.217 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.183    31.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y21        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611    52.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.492    53.585    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y21        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/C
                         clock pessimism              0.000    53.585    
                         clock uncertainty           -0.235    53.350    
    SLICE_X100Y21        FDRE (Setup_FFF2_SLICEL_C_R)
                                                     -0.044    53.306    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]
  -------------------------------------------------------------------
                         required time                         53.306    
                         arrival time                         -31.400    
  -------------------------------------------------------------------
                         slack                                 21.906    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.080ns  (logic 0.039ns (48.750%)  route 0.041ns (51.250%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.137ns
    Source Clock Delay      (SCD):    3.587ns
    Clock Pessimism Removal (CPR):    4.544ns
  Clock Net Delay (Source):      1.494ns (routing 0.999ns, distribution 0.495ns)
  Clock Net Delay (Destination): 1.692ns (routing 1.125ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.494     3.587    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y14        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.626 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/Q
                         net (fo=2, routed)           0.041     3.667    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[23]
    SLICE_X102Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.692     8.137    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C
                         clock pessimism             -4.544     3.593    
    SLICE_X102Y14        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.046     3.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]
  -------------------------------------------------------------------
                         required time                         -3.639    
                         arrival time                           3.667    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.052ns (52.525%)  route 0.047ns (47.475%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.146ns
    Source Clock Delay      (SCD):    3.592ns
    Clock Pessimism Removal (CPR):    4.531ns
  Clock Net Delay (Source):      1.499ns (routing 0.999ns, distribution 0.500ns)
  Clock Net Delay (Destination): 1.701ns (routing 1.125ns, distribution 0.576ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.499     3.592    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/rd_clk
    SLICE_X97Y7          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y7          FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.630 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]/Q
                         net (fo=1, routed)           0.026     3.656    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/fifo_dout[5]
    SLICE_X97Y8          LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.014     3.670 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/shift_reg_in[4]_i_1/O
                         net (fo=1, routed)           0.021     3.691    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO_n_11
    SLICE_X97Y8          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.701     8.146    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X97Y8          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[4]/C
                         clock pessimism             -4.531     3.614    
    SLICE_X97Y8          FDCE (Hold_BFF_SLICEM_C_D)
                                                      0.046     3.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.660    
                         arrival time                           3.691    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.085ns  (logic 0.039ns (46.054%)  route 0.046ns (53.946%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.137ns
    Source Clock Delay      (SCD):    3.586ns
    Clock Pessimism Removal (CPR):    4.546ns
  Clock Net Delay (Source):      1.493ns (routing 0.999ns, distribution 0.494ns)
  Clock Net Delay (Destination): 1.692ns (routing 1.125ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.493     3.586    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X97Y5          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y5          FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.625 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[9]/Q
                         net (fo=2, routed)           0.046     3.670    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/fifo_din[8]
    SLICE_X97Y5          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.692     8.137    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X97Y5          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]/C
                         clock pessimism             -4.546     3.592    
    SLICE_X97Y5          FDCE (Hold_CFF2_SLICEM_C_D)
                                                      0.047     3.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.639    
                         arrival time                           3.670    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.174ns  (logic 0.082ns (47.114%)  route 0.092ns (52.885%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.125ns
    Source Clock Delay      (SCD):    4.945ns
    Clock Pessimism Removal (CPR):    5.098ns
  Clock Net Delay (Source):      2.417ns (routing 1.653ns, distribution 0.764ns)
  Clock Net Delay (Destination): 2.712ns (routing 1.824ns, distribution 0.888ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.417     4.945    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X100Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y18        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     5.005 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/Q
                         net (fo=3, routed)           0.070     5.075    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en
    SLICE_X101Y18        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.022     5.097 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in[1]_i_1__1/O
                         net (fo=1, routed)           0.022     5.119    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in[1]_i_1__1_n_0
    SLICE_X101Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.712    10.125    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X101Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[1]/C
                         clock pessimism             -5.098     5.027    
    SLICE_X101Y18        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     5.087    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.087    
                         arrival time                           5.119    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.082ns (46.579%)  route 0.094ns (53.421%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.125ns
    Source Clock Delay      (SCD):    4.945ns
    Clock Pessimism Removal (CPR):    5.098ns
  Clock Net Delay (Source):      2.417ns (routing 1.653ns, distribution 0.764ns)
  Clock Net Delay (Destination): 2.712ns (routing 1.824ns, distribution 0.888ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.417     4.945    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X100Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y18        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     5.005 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/Q
                         net (fo=3, routed)           0.070     5.075    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en
    SLICE_X101Y18        LUT3 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.022     5.097 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in[0]_i_1__1/O
                         net (fo=1, routed)           0.024     5.121    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in[0]_i_1__1_n_0
    SLICE_X101Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.712    10.125    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X101Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[0]/C
                         clock pessimism             -5.098     5.027    
    SLICE_X101Y18        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     5.087    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_reg_in_reg[0]
  -------------------------------------------------------------------
                         required time                         -5.087    
                         arrival time                           5.121    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.058ns (32.329%)  route 0.121ns (67.671%))
  Logic Levels:           0  
  Clock Path Skew:        0.083ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.116ns
    Source Clock Delay      (SCD):    4.935ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Net Delay (Source):      2.407ns (routing 1.653ns, distribution 0.754ns)
  Clock Net Delay (Destination): 2.703ns (routing 1.824ns, distribution 0.879ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407     4.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y18         FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     4.993 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/Q
                         net (fo=4, routed)           0.121     5.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iCORE_ID[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.703    10.116    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism             -5.099     5.017    
    SLICE_X99Y19         FDCE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     5.079    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         -5.079    
                         arrival time                           5.114    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.125ns
    Source Clock Delay      (SCD):    3.580ns
    Clock Pessimism Removal (CPR):    4.532ns
  Clock Net Delay (Source):      1.487ns (routing 0.999ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.680ns (routing 1.125ns, distribution 0.555ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.487     3.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y16         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.619 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/Q
                         net (fo=2, routed)           0.058     3.677    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[2]
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.680     8.125    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
                         clock pessimism             -4.532     3.593    
    SLICE_X98Y17         FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     3.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.640    
                         arrival time                           3.677    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.094ns  (logic 0.059ns (62.916%)  route 0.035ns (37.084%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.141ns
    Source Clock Delay      (SCD):    3.593ns
    Clock Pessimism Removal (CPR):    4.538ns
  Clock Net Delay (Source):      1.500ns (routing 0.999ns, distribution 0.501ns)
  Clock Net Delay (Destination): 1.696ns (routing 1.125ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.500     3.593    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y7          FDPE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.632 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/Q
                         net (fo=4, routed)           0.029     3.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gc0.count_reg[0]
    SLICE_X98Y7          LUT4 (Prop_D5LUT_SLICEL_I3_O)
                                                      0.020     3.680 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state[1]_i_1/O
                         net (fo=1, routed)           0.006     3.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/next_fwft_state__0[1]
    SLICE_X98Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.696     8.141    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
                         clock pessimism             -4.538     3.603    
    SLICE_X98Y7          FDCE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     3.650    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.650    
                         arrival time                           3.686    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[20]/D
                            (rising edge-triggered cell FDSE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.195ns  (logic 0.090ns (46.170%)  route 0.105ns (53.830%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.095ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.128ns
    Source Clock Delay      (SCD):    4.935ns
    Clock Pessimism Removal (CPR):    5.098ns
  Clock Net Delay (Source):      2.407ns (routing 1.653ns, distribution 0.754ns)
  Clock Net Delay (Destination): 2.715ns (routing 1.824ns, distribution 0.891ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407     4.935    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X103Y26        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y26        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     4.993 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[21]/Q
                         net (fo=2, routed)           0.096     5.089    dbg_hub/inst/BSCANID.u_xsdbm_id/bscanid[21]
    SLICE_X102Y25        LUT4 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.032     5.121 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[20]_i_1/O
                         net (fo=1, routed)           0.009     5.130    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[20]
    SLICE_X102Y25        FDSE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.715    10.128    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X102Y25        FDSE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[20]/C
                         clock pessimism             -5.098     5.030    
    SLICE_X102Y25        FDSE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     5.092    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[20]
  -------------------------------------------------------------------
                         required time                         -5.092    
                         arrival time                           5.130    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.182ns  (logic 0.057ns (31.269%)  route 0.125ns (68.731%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.114ns
    Source Clock Delay      (SCD):    4.936ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Net Delay (Source):      2.408ns (routing 1.653ns, distribution 0.755ns)
  Clock Net Delay (Destination): 2.701ns (routing 1.824ns, distribution 0.877ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.408     4.936    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y19         FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.993 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/Q
                         net (fo=5, routed)           0.125     5.118    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/Q[3]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.701    10.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism             -5.099     5.015    
    SLICE_X97Y18         FDCE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     5.077    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         -5.077    
                         arrival time                           5.118    
  -------------------------------------------------------------------
                         slack                                  0.040    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
Waveform(ns):       { 0.000 25.000 }
Period(ns):         50.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I    n/a            1.290         50.000      48.710     BUFGCE_X0Y164  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X96Y5    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  default_sysclk_c0_300mhz_clk_p
  To Clock:  default_sysclk_c0_300mhz_clk_p

Setup :            0  Failing Endpoints,  Worst Slack        1.969ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.042ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.969ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.235ns  (logic 0.081ns (6.557%)  route 1.154ns (93.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.510ns = ( 4.844 - 3.334 ) 
    Source Clock Delay      (SCD):    1.763ns
    Clock Pessimism Removal (CPR):    0.232ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.730ns (routing 0.001ns, distribution 0.729ns)
  Clock Net Delay (Destination): 0.645ns (routing 0.001ns, distribution 0.644ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.730     1.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.154     2.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.645     4.844    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism              0.232     5.076    
                         clock uncertainty           -0.035     5.041    
    SLICE_X81Y111        FDSE (Setup_FFF_SLICEL_C_S)
                                                     -0.074     4.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                          4.967    
                         arrival time                          -2.998    
  -------------------------------------------------------------------
                         slack                                  1.969    

Slack (MET) :             1.969ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.235ns  (logic 0.081ns (6.557%)  route 1.154ns (93.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.510ns = ( 4.844 - 3.334 ) 
    Source Clock Delay      (SCD):    1.763ns
    Clock Pessimism Removal (CPR):    0.232ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.730ns (routing 0.001ns, distribution 0.729ns)
  Clock Net Delay (Destination): 0.645ns (routing 0.001ns, distribution 0.644ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.730     1.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.154     2.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.645     4.844    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism              0.232     5.076    
                         clock uncertainty           -0.035     5.041    
    SLICE_X81Y111        FDSE (Setup_HFF_SLICEL_C_S)
                                                     -0.074     4.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                          4.967    
                         arrival time                          -2.998    
  -------------------------------------------------------------------
                         slack                                  1.969    

Slack (MET) :             1.969ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/S
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.235ns  (logic 0.081ns (6.557%)  route 1.154ns (93.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.510ns = ( 4.844 - 3.334 ) 
    Source Clock Delay      (SCD):    1.763ns
    Clock Pessimism Removal (CPR):    0.232ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.730ns (routing 0.001ns, distribution 0.729ns)
  Clock Net Delay (Destination): 0.645ns (routing 0.001ns, distribution 0.644ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.730     1.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.154     2.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/S
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.645     4.844    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism              0.232     5.076    
                         clock uncertainty           -0.035     5.041    
    SLICE_X81Y111        FDSE (Setup_HFF2_SLICEL_C_S)
                                                     -0.074     4.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                          4.967    
                         arrival time                          -2.998    
  -------------------------------------------------------------------
                         slack                                  1.969    

Slack (MET) :             2.026ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.190ns  (logic 0.240ns (20.165%)  route 0.950ns (79.835%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.508ns = ( 4.842 - 3.334 ) 
    Source Clock Delay      (SCD):    1.773ns
    Clock Pessimism Removal (CPR):    0.257ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.740ns (routing 0.001ns, distribution 0.739ns)
  Clock Net Delay (Destination): 0.643ns (routing 0.001ns, distribution 0.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.740     1.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.854 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.588     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y111        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.565 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.058     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y110        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.304     2.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.643     4.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                         clock pessimism              0.257     5.099    
                         clock uncertainty           -0.035     5.064    
    SLICE_X81Y111        FDRE (Setup_BFF2_SLICEL_C_R)
                                                     -0.074     4.990    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]
  -------------------------------------------------------------------
                         required time                          4.990    
                         arrival time                          -2.963    
  -------------------------------------------------------------------
                         slack                                  2.026    

Slack (MET) :             2.026ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.190ns  (logic 0.240ns (20.165%)  route 0.950ns (79.835%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.508ns = ( 4.842 - 3.334 ) 
    Source Clock Delay      (SCD):    1.773ns
    Clock Pessimism Removal (CPR):    0.257ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.740ns (routing 0.001ns, distribution 0.739ns)
  Clock Net Delay (Destination): 0.643ns (routing 0.001ns, distribution 0.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.740     1.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.854 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.588     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y111        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.565 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.058     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y110        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.304     2.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.643     4.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.257     5.099    
                         clock uncertainty           -0.035     5.064    
    SLICE_X81Y111        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.074     4.990    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          4.990    
                         arrival time                          -2.963    
  -------------------------------------------------------------------
                         slack                                  2.026    

Slack (MET) :             2.026ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.190ns  (logic 0.240ns (20.165%)  route 0.950ns (79.835%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.508ns = ( 4.842 - 3.334 ) 
    Source Clock Delay      (SCD):    1.773ns
    Clock Pessimism Removal (CPR):    0.257ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.740ns (routing 0.001ns, distribution 0.739ns)
  Clock Net Delay (Destination): 0.643ns (routing 0.001ns, distribution 0.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.740     1.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.854 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.588     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y111        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.565 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.058     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y110        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.304     2.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.643     4.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.257     5.099    
                         clock uncertainty           -0.035     5.064    
    SLICE_X81Y111        FDRE (Setup_DFF2_SLICEL_C_R)
                                                     -0.074     4.990    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          4.990    
                         arrival time                          -2.963    
  -------------------------------------------------------------------
                         slack                                  2.026    

Slack (MET) :             2.026ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.190ns  (logic 0.240ns (20.165%)  route 0.950ns (79.835%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.508ns = ( 4.842 - 3.334 ) 
    Source Clock Delay      (SCD):    1.773ns
    Clock Pessimism Removal (CPR):    0.257ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.740ns (routing 0.001ns, distribution 0.739ns)
  Clock Net Delay (Destination): 0.643ns (routing 0.001ns, distribution 0.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.740     1.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.854 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.588     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y111        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.565 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.058     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y110        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.304     2.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.643     4.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.257     5.099    
                         clock uncertainty           -0.035     5.064    
    SLICE_X81Y111        FDRE (Setup_AFF_SLICEL_C_R)
                                                     -0.074     4.990    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          4.990    
                         arrival time                          -2.963    
  -------------------------------------------------------------------
                         slack                                  2.026    

Slack (MET) :             2.046ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.269ns  (logic 0.353ns (27.814%)  route 0.916ns (72.186%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.508ns = ( 4.842 - 3.334 ) 
    Source Clock Delay      (SCD):    1.773ns
    Clock Pessimism Removal (CPR):    0.257ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.740ns (routing 0.001ns, distribution 0.739ns)
  Clock Net Delay (Destination): 0.643ns (routing 0.001ns, distribution 0.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.740     1.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.854 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.588     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y111        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.565 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.078     2.643    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y111        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     2.792 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_2/O
                         net (fo=1, routed)           0.250     3.042    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[6]
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.643     4.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.257     5.099    
                         clock uncertainty           -0.035     5.064    
    SLICE_X81Y111        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     5.089    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          5.089    
                         arrival time                          -3.042    
  -------------------------------------------------------------------
                         slack                                  2.046    

Slack (MET) :             2.223ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.093ns  (logic 0.081ns (7.411%)  route 1.012ns (92.589%))
  Logic Levels:           0  
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.503ns = ( 4.837 - 3.334 ) 
    Source Clock Delay      (SCD):    1.763ns
    Clock Pessimism Removal (CPR):    0.251ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.730ns (routing 0.001ns, distribution 0.729ns)
  Clock Net Delay (Destination): 0.638ns (routing 0.001ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.730     1.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y113        FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     1.844 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/Q
                         net (fo=1, routed)           1.012     2.856    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[0]
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.638     4.837    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                         clock pessimism              0.251     5.089    
                         clock uncertainty           -0.035     5.053    
    SLICE_X81Y113        FDPE (Setup_BFF2_SLICEL_C_D)
                                                      0.025     5.078    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]
  -------------------------------------------------------------------
                         required time                          5.078    
                         arrival time                          -2.856    
  -------------------------------------------------------------------
                         slack                                  2.223    

Slack (MET) :             2.237ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.048ns  (logic 0.246ns (23.473%)  route 0.802ns (76.527%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.039ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.538ns = ( 4.872 - 3.334 ) 
    Source Clock Delay      (SCD):    1.762ns
    Clock Pessimism Removal (CPR):    0.185ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.729ns (routing 0.001ns, distribution 0.728ns)
  Clock Net Delay (Destination): 0.673ns (routing 0.001ns, distribution 0.672ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.729     1.762    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y110        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y110        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     1.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           0.154     1.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X81Y107        LUT3 (Prop_B5LUT_SLICEL_I1_O)
                                                      0.165     2.162 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.648     2.810    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.835 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.875 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.673     4.872    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                         clock pessimism              0.185     5.057    
                         clock uncertainty           -0.035     5.022    
    SLICE_X95Y103        FDRE (Setup_AFF2_SLICEL_C_D)
                                                      0.025     5.047    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg
  -------------------------------------------------------------------
                         required time                          5.047    
                         arrival time                          -2.810    
  -------------------------------------------------------------------
                         slack                                  2.237    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.095ns  (logic 0.059ns (61.858%)  route 0.036ns (38.142%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.261ns
    Source Clock Delay      (SCD):    1.028ns
    Clock Pessimism Removal (CPR):    0.227ns
  Clock Net Delay (Source):      0.421ns (routing 0.000ns, distribution 0.421ns)
  Clock Net Delay (Destination): 0.481ns (routing 0.001ns, distribution 0.480ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.421     1.028    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDSE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.067 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.030     1.097    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y111        LUT4 (Prop_H5LUT_SLICEL_I2_O)
                                                      0.020     1.117 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1/O
                         net (fo=1, routed)           0.006     1.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1_n_0
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.481     1.261    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism             -0.227     1.034    
    SLICE_X81Y111        FDSE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.081    
                         arrival time                           1.123    
  -------------------------------------------------------------------
                         slack                                  0.042    

Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.072ns (70.006%)  route 0.031ns (29.994%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.257ns
    Source Clock Delay      (SCD):    1.025ns
    Clock Pessimism Removal (CPR):    0.226ns
  Clock Net Delay (Source):      0.418ns (routing 0.000ns, distribution 0.418ns)
  Clock Net Delay (Destination): 0.477ns (routing 0.001ns, distribution 0.476ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.418     1.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.064 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.025     1.089    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X81Y111        LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     1.122 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.006     1.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.477     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism             -0.226     1.031    
    SLICE_X81Y111        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.078    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.078    
                         arrival time                           1.128    
  -------------------------------------------------------------------
                         slack                                  0.050    

Slack (MET) :             0.057ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.109ns  (logic 0.062ns (56.684%)  route 0.047ns (43.316%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.261ns
    Source Clock Delay      (SCD):    1.028ns
    Clock Pessimism Removal (CPR):    0.227ns
  Clock Net Delay (Source):      0.421ns (routing 0.000ns, distribution 0.421ns)
  Clock Net Delay (Destination): 0.481ns (routing 0.001ns, distribution 0.480ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.421     1.028    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDSE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.067 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.030     1.097    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y111        LUT4 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     1.120 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.017     1.137    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.481     1.261    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism             -0.227     1.034    
    SLICE_X81Y111        FDSE (Hold_HFF_SLICEL_C_D)
                                                      0.046     1.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.080    
                         arrival time                           1.137    
  -------------------------------------------------------------------
                         slack                                  0.057    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.119ns  (logic 0.059ns (49.550%)  route 0.060ns (50.450%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.253ns
    Source Clock Delay      (SCD):    1.028ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Net Delay (Source):      0.421ns (routing 0.000ns, distribution 0.421ns)
  Clock Net Delay (Destination): 0.473ns (routing 0.001ns, distribution 0.472ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.421     1.028    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDSE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.067 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/Q
                         net (fo=7, routed)           0.054     1.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]
    SLICE_X81Y110        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.020     1.141 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.006     1.147    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X81Y110        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.473     1.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y110        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism             -0.214     1.039    
    SLICE_X81Y110        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.086    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                         -1.086    
                         arrival time                           1.147    
  -------------------------------------------------------------------
                         slack                                  0.061    

Slack (MET) :             0.063ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.115ns  (logic 0.074ns (64.433%)  route 0.041ns (35.567%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.257ns
    Source Clock Delay      (SCD):    1.025ns
    Clock Pessimism Removal (CPR):    0.226ns
  Clock Net Delay (Source):      0.418ns (routing 0.000ns, distribution 0.418ns)
  Clock Net Delay (Destination): 0.477ns (routing 0.001ns, distribution 0.476ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.418     1.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.064 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.025     1.089    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X81Y111        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.124 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.016     1.140    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.477     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism             -0.226     1.031    
    SLICE_X81Y111        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.077    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.077    
                         arrival time                           1.140    
  -------------------------------------------------------------------
                         slack                                  0.063    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.254ns
    Source Clock Delay      (SCD):    1.022ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      0.415ns (routing 0.000ns, distribution 0.415ns)
  Clock Net Delay (Destination): 0.474ns (routing 0.001ns, distribution 0.473ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.415     1.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.062 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/Q
                         net (fo=1, routed)           0.081     1.143    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[0]
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.474     1.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                         clock pessimism             -0.225     1.028    
    SLICE_X81Y114        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.075    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.075    
                         arrival time                           1.143    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.787%)  route 0.082ns (67.213%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.254ns
    Source Clock Delay      (SCD):    1.022ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      0.415ns (routing 0.000ns, distribution 0.415ns)
  Clock Net Delay (Destination): 0.474ns (routing 0.001ns, distribution 0.473ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.415     1.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.062 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/Q
                         net (fo=1, routed)           0.082     1.144    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[2]
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.474     1.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                         clock pessimism             -0.225     1.028    
    SLICE_X81Y114        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.075    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.075    
                         arrival time                           1.144    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.072ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.124ns  (logic 0.079ns (63.788%)  route 0.045ns (36.212%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.261ns
    Source Clock Delay      (SCD):    1.028ns
    Clock Pessimism Removal (CPR):    0.227ns
  Clock Net Delay (Source):      0.421ns (routing 0.000ns, distribution 0.421ns)
  Clock Net Delay (Destination): 0.481ns (routing 0.001ns, distribution 0.480ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.421     1.028    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y111        FDSE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.067 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.027     1.094    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X81Y111        LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.040     1.134 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.018     1.152    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.481     1.261    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y111        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.227     1.034    
    SLICE_X81Y111        FDSE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.080    
                         arrival time                           1.152    
  -------------------------------------------------------------------
                         slack                                  0.072    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.040ns (23.952%)  route 0.127ns (76.048%))
  Logic Levels:           0  
  Clock Path Skew:        0.018ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.254ns
    Source Clock Delay      (SCD):    1.021ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Net Delay (Source):      0.414ns (routing 0.000ns, distribution 0.414ns)
  Clock Net Delay (Destination): 0.474ns (routing 0.001ns, distribution 0.473ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.414     1.021    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y113        FDPE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.061 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/Q
                         net (fo=1, routed)           0.127     1.188    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[1]
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.474     1.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                         clock pessimism             -0.214     1.039    
    SLICE_X81Y114        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.047     1.086    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.086    
                         arrival time                           1.188    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.118ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.040ns (23.392%)  route 0.131ns (76.608%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.254ns
    Source Clock Delay      (SCD):    1.022ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      0.415ns (routing 0.000ns, distribution 0.415ns)
  Clock Net Delay (Destination): 0.474ns (routing 0.001ns, distribution 0.473ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.415     1.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.062 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/Q
                         net (fo=1, routed)           0.131     1.193    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[1]
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.474     1.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                         clock pessimism             -0.225     1.028    
    SLICE_X81Y114        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.047     1.075    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.075    
                         arrival time                           1.193    
  -------------------------------------------------------------------
                         slack                                  0.118    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         default_sysclk_c0_300mhz_clk_p
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.334
Sources:            { default_sysclk_c0_300mhz_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I           n/a            1.290         3.334       2.044      BUFGCE_X0Y46   d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.334       2.263      MMCM_X0Y1      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y110  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.334       96.666     MMCM_X0Y1      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y111  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.038ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.011ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid2vector_q_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.176ns (6.422%)  route 2.564ns (93.578%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.184ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.336ns = ( 6.337 - 3.001 ) 
    Source Clock Delay      (SCD):    3.047ns
    Clock Pessimism Removal (CPR):    -0.474ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.830ns (routing 0.764ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.577ns (routing 0.695ns, distribution 0.882ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.830     3.047    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aclk
    SLICE_X57Y57         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y57         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.127 f  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/Q
                         net (fo=37, routed)          2.514     5.641    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/SS[0]
    SLICE_X74Y72         LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.096     5.737 r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid2vector_q_i_1__0/O
                         net (fo=1, routed)           0.050     5.787    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid2vector_q_i_1__0_n_0
    SLICE_X74Y72         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid2vector_q_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.577     6.337    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/aclk
    SLICE_X74Y72         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid2vector_q_reg/C
                         clock pessimism             -0.474     5.863    
                         clock uncertainty           -0.062     5.801    
    SLICE_X74Y72         FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025     5.826    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid2vector_q_reg
  -------------------------------------------------------------------
                         required time                          5.826    
                         arrival time                          -5.787    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.132ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[47]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.708ns  (logic 0.930ns (34.340%)  route 1.778ns (65.660%))
  Logic Levels:           7  (CARRY8=1 LUT3=1 LUT6=5)
  Clock Path Skew:        -0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.179ns = ( 6.180 - 3.001 ) 
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.651ns (routing 0.764ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.420ns (routing 0.695ns, distribution 0.725ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.651     2.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X83Y86         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y86         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.947 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/Q
                         net (fo=11, routed)          0.181     3.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]_0[1]_repN
    SLICE_X82Y84         LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     3.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_18__2/O
                         net (fo=1, routed)           0.207     3.483    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_18__2_n_0
    SLICE_X83Y87         LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.125     3.608 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.016     3.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X83Y87         CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[5])
                                                      0.199     3.823 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.436     4.259    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X88Y90         LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     4.382 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__0/O
                         net (fo=4, routed)           0.100     4.482    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__0_n_0
    SLICE_X88Y92         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     4.517 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=77, routed)          0.423     4.940    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X86Y87         LUT3 (Prop_B5LUT_SLICEM_I1_O)
                                                      0.072     5.012 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_3__2/O
                         net (fo=31, routed)          0.366     5.379    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_3__2_n_0
    SLICE_X88Y90         LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     5.528 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_1__0/O
                         net (fo=1, routed)           0.048     5.576    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_1__0_n_0
    SLICE_X88Y90         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.420     6.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X88Y90         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[47]/C
                         clock pessimism             -0.434     5.746    
                         clock uncertainty           -0.062     5.683    
    SLICE_X88Y90         FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.025     5.708    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[47]
  -------------------------------------------------------------------
                         required time                          5.708    
                         arrival time                          -5.576    
  -------------------------------------------------------------------
                         slack                                  0.132    

Slack (MET) :             0.137ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_rd_addrb/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.744ns  (logic 0.204ns (7.433%)  route 2.540ns (92.567%))
  Logic Levels:           1  (RAMD32=1)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 6.289 - 3.001 ) 
    Source Clock Delay      (SCD):    2.941ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.724ns (routing 0.764ns, distribution 0.960ns)
  Clock Net Delay (Destination): 1.529ns (routing 0.695ns, distribution 0.834ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.724     2.941    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_rd_addrb/s_sc_aclk
    SLICE_X77Y19         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_rd_addrb/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y19         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     3.022 r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_rd_addrb/count_r_reg[1]/Q
                         net (fo=144, routed)         2.481     5.503    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/ADDRG1
    SLICE_X79Y23         RAMD32 (Prop_G6LUT_SLICEM_RADR1_O)
                                                      0.123     5.626 r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/O
                         net (fo=1, routed)           0.059     5.685    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0[41]
    SLICE_X79Y23         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.529     6.289    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X79Y23         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]/C
                         clock pessimism             -0.430     5.859    
                         clock uncertainty           -0.062     5.797    
    SLICE_X79Y23         FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     5.822    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]
  -------------------------------------------------------------------
                         required time                          5.822    
                         arrival time                          -5.685    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.138ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica_1/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.759ns  (logic 0.680ns (24.645%)  route 2.079ns (75.355%))
  Logic Levels:           7  (CARRY8=1 LUT3=1 LUT6=5)
  Clock Path Skew:        -0.066ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.205ns = ( 6.205 - 3.001 ) 
    Source Clock Delay      (SCD):    2.837ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.620ns (routing 0.764ns, distribution 0.856ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.695ns, distribution 0.750ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.620     2.837    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X86Y85         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y85         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica_1/Q
                         net (fo=5, routed)           0.400     3.316    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]_repN_1
    SLICE_X84Y84         LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     3.351 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.186     3.537    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X83Y87         LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.037     3.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.016     3.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X83Y87         CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[5])
                                                      0.199     3.789 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.436     4.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X88Y90         LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     4.349 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__0/O
                         net (fo=4, routed)           0.100     4.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__0_n_0
    SLICE_X88Y92         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     4.484 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=77, routed)          0.423     4.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X86Y87         LUT3 (Prop_B5LUT_SLICEM_I1_O)
                                                      0.072     4.979 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_3__2/O
                         net (fo=31, routed)          0.160     5.139    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_3__2_n_0
    SLICE_X86Y86         LUT6 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.100     5.239 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[0]_i_1__0/O
                         net (fo=3, routed)           0.357     5.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[0]_i_1__0_n_0
    SLICE_X83Y86         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.445     6.205    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X83Y86         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica/C
                         clock pessimism             -0.434     5.771    
                         clock uncertainty           -0.062     5.709    
    SLICE_X83Y86         FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     5.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica
  -------------------------------------------------------------------
                         required time                          5.734    
                         arrival time                          -5.596    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.147ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_stall_d]/R
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.518ns  (logic 0.080ns (3.177%)  route 2.438ns (96.823%))
  Logic Levels:           0  
  Clock Path Skew:        -0.199ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.321ns = ( 6.322 - 3.001 ) 
    Source Clock Delay      (SCD):    3.047ns
    Clock Pessimism Removal (CPR):    -0.474ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.830ns (routing 0.764ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.562ns (routing 0.695ns, distribution 0.867ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.830     3.047    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aclk
    SLICE_X57Y57         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y57         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.127 r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/Q
                         net (fo=37, routed)          2.438     5.565    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/SS[0]
    SLICE_X80Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_stall_d]/R
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.562     6.322    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/aclk
    SLICE_X80Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_stall_d]/C
                         clock pessimism             -0.474     5.848    
                         clock uncertainty           -0.062     5.786    
    SLICE_X80Y67         FDRE (Setup_AFF_SLICEL_C_R)
                                                     -0.074     5.712    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_stall_d]
  -------------------------------------------------------------------
                         required time                          5.712    
                         arrival time                          -5.565    
  -------------------------------------------------------------------
                         slack                                  0.147    

Slack (MET) :             0.147ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i_reg[1025]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer_reg[184]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.650ns  (logic 0.567ns (21.395%)  route 2.083ns (78.605%))
  Logic Levels:           4  (LUT2=1 LUT5=2 LUT6=1)
  Clock Path Skew:        -0.166ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.463ns = ( 6.464 - 3.001 ) 
    Source Clock Delay      (SCD):    3.218ns
    Clock Pessimism Removal (CPR):    -0.411ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.001ns (routing 0.764ns, distribution 1.237ns)
  Clock Net Delay (Destination): 1.704ns (routing 0.695ns, distribution 1.009ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       2.001     3.218    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/aclk
    SLICE_X32Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i_reg[1025]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y67         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.299 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i_reg[1025]/Q
                         net (fo=31, routed)          0.731     4.030    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/s_axi_arburst[1]
    SLICE_X38Y61         LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     4.153 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[1132]_i_2__0/O
                         net (fo=17, routed)          0.514     4.667    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/m_vector_i_reg[1025]
    SLICE_X36Y61         LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.149     4.816 f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[185]_i_9/O
                         net (fo=1, routed)           0.486     5.302    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[185]_i_9_n_0
    SLICE_X38Y62         LUT5 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.124     5.426 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[185]_i_4__0/O
                         net (fo=3, routed)           0.102     5.529    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[185]_i_4__0_n_0
    SLICE_X38Y63         LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.090     5.619 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[184]_i_1__0/O
                         net (fo=2, routed)           0.249     5.868    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/s_ar_payld[184]
    SLICE_X38Y63         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer_reg[184]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.704     6.464    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/aclk
    SLICE_X38Y63         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer_reg[184]/C
                         clock pessimism             -0.411     6.053    
                         clock uncertainty           -0.062     5.990    
    SLICE_X38Y63         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     6.015    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer_reg[184]
  -------------------------------------------------------------------
                         required time                          6.015    
                         arrival time                          -5.868    
  -------------------------------------------------------------------
                         slack                                  0.147    

Slack (MET) :             0.150ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[m_valid_i]/R
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.517ns  (logic 0.080ns (3.179%)  route 2.437ns (96.821%))
  Logic Levels:           0  
  Clock Path Skew:        -0.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.323ns = ( 6.324 - 3.001 ) 
    Source Clock Delay      (SCD):    3.047ns
    Clock Pessimism Removal (CPR):    -0.474ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.830ns (routing 0.764ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.695ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.830     3.047    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aclk
    SLICE_X57Y57         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y57         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.127 r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/Q
                         net (fo=37, routed)          2.437     5.564    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/SS[0]
    SLICE_X80Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[m_valid_i]/R
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.564     6.324    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/aclk
    SLICE_X80Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[m_valid_i]/C
                         clock pessimism             -0.474     5.850    
                         clock uncertainty           -0.062     5.788    
    SLICE_X80Y67         FDRE (Setup_HFF_SLICEL_C_R)
                                                     -0.074     5.714    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[m_valid_i]
  -------------------------------------------------------------------
                         required time                          5.714    
                         arrival time                          -5.564    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.150ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_ready_i]/R
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.517ns  (logic 0.080ns (3.179%)  route 2.437ns (96.821%))
  Logic Levels:           0  
  Clock Path Skew:        -0.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.323ns = ( 6.324 - 3.001 ) 
    Source Clock Delay      (SCD):    3.047ns
    Clock Pessimism Removal (CPR):    -0.474ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.830ns (routing 0.764ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.695ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.830     3.047    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aclk
    SLICE_X57Y57         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y57         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.127 r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/areset_reg/Q
                         net (fo=37, routed)          2.437     5.564    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/SS[0]
    SLICE_X80Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_ready_i]/R
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.564     6.324    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/aclk
    SLICE_X80Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_ready_i]/C
                         clock pessimism             -0.474     5.850    
                         clock uncertainty           -0.062     5.788    
    SLICE_X80Y67         FDRE (Setup_HFF2_SLICEL_C_R)
                                                     -0.074     5.714    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/state_reg[s_ready_i]
  -------------------------------------------------------------------
                         required time                          5.714    
                         arrival time                          -5.564    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.151ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i_reg[1025]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/shift_reg_reg[0]_srl16/D
                            (rising edge-triggered cell SRL16E clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.472ns  (logic 0.377ns (15.253%)  route 2.095ns (84.747%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.249ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.442ns = ( 6.443 - 3.001 ) 
    Source Clock Delay      (SCD):    3.218ns
    Clock Pessimism Removal (CPR):    -0.474ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.001ns (routing 0.764ns, distribution 1.237ns)
  Clock Net Delay (Destination): 1.683ns (routing 0.695ns, distribution 0.988ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       2.001     3.218    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/aclk
    SLICE_X32Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i_reg[1025]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y67         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.299 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i_reg[1025]/Q
                         net (fo=31, routed)          0.731     4.030    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/s_axi_arburst[1]
    SLICE_X38Y61         LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     4.153 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/ar_reg_slice/skid_buffer[1132]_i_2__0/O
                         net (fo=17, routed)          0.600     4.753    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/skid_buffer_reg[1127]_1
    SLICE_X35Y62         LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     4.876 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/skid_buffer[1127]_i_2__0/O
                         net (fo=1, routed)           0.085     4.961    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/skid_buffer[1127]_i_2__0_n_0
    SLICE_X36Y62         LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.050     5.011 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/skid_buffer[1127]_i_1__0/O
                         net (fo=6, routed)           0.679     5.689    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/m_vector_i_reg[1028][0]
    SLICE_X41Y55         SRL16E                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/shift_reg_reg[0]_srl16/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.683     6.443    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/aclk
    SLICE_X41Y55         SRL16E                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/shift_reg_reg[0]_srl16/CLK
                         clock pessimism             -0.474     5.969    
                         clock uncertainty           -0.062     5.907    
    SLICE_X41Y55         SRL16E (Setup_G6LUT_SLICEM_CLK_D)
                                                     -0.067     5.840    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/gen_thread_loop[0].r_payld_fifo/cmd_fifo/gen_srls[2].srl_nx1/shift_reg_reg[0]_srl16
  -------------------------------------------------------------------
                         required time                          5.840    
                         arrival time                          -5.689    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.151ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[35]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.716ns  (logic 0.833ns (30.673%)  route 1.883ns (69.327%))
  Logic Levels:           7  (CARRY8=1 LUT3=1 LUT6=5)
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.205ns = ( 6.206 - 3.001 ) 
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.651ns (routing 0.764ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.446ns (routing 0.695ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.651     2.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X83Y86         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y86         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.947 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[1]_replica/Q
                         net (fo=11, routed)          0.181     3.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]_0[1]_repN
    SLICE_X82Y84         LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     3.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_18__2/O
                         net (fo=1, routed)           0.207     3.483    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_18__2_n_0
    SLICE_X83Y87         LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.125     3.608 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.016     3.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X83Y87         CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[5])
                                                      0.199     3.823 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.436     4.259    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X88Y90         LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     4.382 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__0/O
                         net (fo=4, routed)           0.100     4.482    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__0_n_0
    SLICE_X88Y92         LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     4.517 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=77, routed)          0.423     4.940    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X86Y87         LUT3 (Prop_B5LUT_SLICEM_I1_O)
                                                      0.072     5.012 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_3__2/O
                         net (fo=31, routed)          0.460     5.472    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_3__2_n_0
    SLICE_X82Y80         LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.052     5.524 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[35]_i_1__0/O
                         net (fo=1, routed)           0.059     5.583    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[35]_i_1__0_n_0
    SLICE_X82Y80         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[35]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.446     6.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X82Y80         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[35]/C
                         clock pessimism             -0.434     5.771    
                         clock uncertainty           -0.062     5.709    
    SLICE_X82Y80         FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     5.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[35]
  -------------------------------------------------------------------
                         required time                          5.734    
                         arrival time                          -5.583    
  -------------------------------------------------------------------
                         slack                                  0.151    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[35]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.040ns (21.164%)  route 0.149ns (78.836%))
  Logic Levels:           0  
  Clock Path Skew:        0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.788ns
    Source Clock Delay      (SCD):    1.884ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      0.879ns (routing 0.421ns, distribution 0.458ns)
  Clock Net Delay (Destination): 1.125ns (routing 0.473ns, distribution 0.652ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.879     1.884    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y25         FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[35]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y25         FDSE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.924 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[35]/Q
                         net (fo=1, routed)           0.149     2.073    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y22 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.125     1.788    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/div_clk
    BITSLICE_RX_TX_X0Y22 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.242     2.030    
    BITSLICE_RX_TX_X0Y22 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.032     2.062    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.062    
                         arrival time                           2.073    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1302]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_138/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.172ns  (logic 0.058ns (33.721%)  route 0.114ns (66.279%))
  Logic Levels:           0  
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.003ns
    Source Clock Delay      (SCD):    3.288ns
    Clock Pessimism Removal (CPR):    -0.369ns
  Clock Net Delay (Source):      1.528ns (routing 0.695ns, distribution 0.833ns)
  Clock Net Delay (Destination): 1.786ns (routing 0.764ns, distribution 1.022ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.528     3.288    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/r_reg/aclk
    SLICE_X80Y18         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1302]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y18         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.346 r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1302]/Q
                         net (fo=1, routed)           0.114     3.460    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_138/DIA0
    SLICE_X79Y18         RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_138/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.786     3.003    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_138/WCLK
    SLICE_X79Y18         RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_138/RAMA/CLK
                         clock pessimism              0.369     3.372    
    SLICE_X79Y18         RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     3.447    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_138/RAMA
  -------------------------------------------------------------------
                         required time                         -3.447    
                         arrival time                           3.460    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[152].srl_nx1/shift_reg_reg[0]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.038ns (38.213%)  route 0.061ns (61.787%))
  Logic Levels:           0  
  Clock Path Skew:        0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.858ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    -0.223ns
  Clock Net Delay (Source):      1.035ns (routing 0.421ns, distribution 0.614ns)
  Clock Net Delay (Destination): 1.195ns (routing 0.473ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.035     2.040    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X53Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y67         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.078 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][24]/Q
                         net (fo=2, routed)           0.061     2.139    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[152].srl_nx1/s_mesg[0]
    SLICE_X53Y66         SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[152].srl_nx1/shift_reg_reg[0]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.195     1.858    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[152].srl_nx1/aclk
    SLICE_X53Y66         SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[152].srl_nx1/shift_reg_reg[0]_srl32/CLK
                         clock pessimism              0.223     2.081    
    SLICE_X53Y66         SRLC32E (Hold_D6LUT_SLICEM_CLK_D)
                                                      0.046     2.127    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[152].srl_nx1/shift_reg_reg[0]_srl32
  -------------------------------------------------------------------
                         required time                         -2.127    
                         arrival time                           2.139    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][72]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.095ns (53.073%)  route 0.084ns (46.927%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.091ns
    Source Clock Delay      (SCD):    3.400ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Net Delay (Source):      1.641ns (routing 0.695ns, distribution 0.946ns)
  Clock Net Delay (Destination): 1.874ns (routing 0.764ns, distribution 1.110ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.641     3.400    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X60Y65         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y65         FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     3.460 r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[72]/Q
                         net (fo=1, routed)           0.062     3.522    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_mux_payld/s_sc_payld[352]
    SLICE_X59Y65         LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.035     3.557 r  d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_mux_payld/gen_pipe[1].pipe[1][72]_i_1/O
                         net (fo=1, routed)           0.022     3.579    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/pipe[0][60]
    SLICE_X59Y65         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][72]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.874     3.091    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X59Y65         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][72]/C
                         clock pessimism              0.413     3.504    
    SLICE_X59Y65         FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     3.564    d_1_i/ddr4/axi_smc_1/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][72]
  -------------------------------------------------------------------
                         required time                         -3.564    
                         arrival time                           3.579    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[44]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.216ns  (logic 0.040ns (18.519%)  route 0.176ns (81.481%))
  Logic Levels:           0  
  Clock Path Skew:        0.151ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.801ns
    Source Clock Delay      (SCD):    1.892ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      0.887ns (routing 0.421ns, distribution 0.466ns)
  Clock Net Delay (Destination): 1.138ns (routing 0.473ns, distribution 0.665ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.887     1.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y2          FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[44]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y2          FDSE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.932 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[44]/Q
                         net (fo=1, routed)           0.176     2.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.138     1.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/div_clk
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.242     2.043    
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.050     2.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.093    
                         arrival time                           2.108    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_write.s_axi_bid_i_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/skid_buffer_reg[1037]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.175ns  (logic 0.079ns (45.021%)  route 0.096ns (54.979%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.227ns
    Source Clock Delay      (SCD):    3.530ns
    Clock Pessimism Removal (CPR):    -0.404ns
  Clock Net Delay (Source):      1.771ns (routing 0.695ns, distribution 1.076ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.764ns, distribution 1.246ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.771     3.530    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/aclk
    SLICE_X23Y75         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_write.s_axi_bid_i_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X23Y75         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     3.587 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_write.s_axi_bid_i_reg[13]/Q
                         net (fo=2, routed)           0.070     3.658    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_write.s_axi_bid_i_reg[15]_0[13]
    SLICE_X24Y75         LUT4 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.022     3.680 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/skid_buffer[1037]_i_1/O
                         net (fo=1, routed)           0.026     3.706    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/D[13]
    SLICE_X24Y75         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/skid_buffer_reg[1037]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       2.010     3.227    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/aclk
    SLICE_X24Y75         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/skid_buffer_reg[1037]/C
                         clock pessimism              0.404     3.630    
    SLICE_X24Y75         FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     3.690    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/skid_buffer_reg[1037]
  -------------------------------------------------------------------
                         required time                         -3.690    
                         arrival time                           3.706    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][28]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[156].srl_nx1/shift_reg_reg[0]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.438%)  route 0.057ns (59.562%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.858ns
    Source Clock Delay      (SCD):    2.039ns
    Clock Pessimism Removal (CPR):    -0.223ns
  Clock Net Delay (Source):      1.034ns (routing 0.421ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.195ns (routing 0.473ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.034     2.039    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X53Y67         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y67         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.078 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][28]/Q
                         net (fo=2, routed)           0.057     2.135    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[156].srl_nx1/s_mesg[0]
    SLICE_X53Y66         SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[156].srl_nx1/shift_reg_reg[0]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.195     1.858    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[156].srl_nx1/aclk
    SLICE_X53Y66         SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[156].srl_nx1/shift_reg_reg[0]_srl32/CLK
                         clock pessimism              0.223     2.081    
    SLICE_X53Y66         SRLC32E (Hold_G6LUT_SLICEM_CLK_D)
                                                      0.039     2.120    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[156].srl_nx1/shift_reg_reg[0]_srl32
  -------------------------------------------------------------------
                         required time                         -2.120    
                         arrival time                           2.135    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[139].srl_nx1/shift_reg_reg[0]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.124%)  route 0.061ns (60.876%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.852ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      1.033ns (routing 0.421ns, distribution 0.612ns)
  Clock Net Delay (Destination): 1.189ns (routing 0.473ns, distribution 0.716ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.033     2.038    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X55Y75         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y75         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.077 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][11]/Q
                         net (fo=2, routed)           0.061     2.138    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[139].srl_nx1/s_mesg[0]
    SLICE_X54Y75         SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[139].srl_nx1/shift_reg_reg[0]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.189     1.852    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[139].srl_nx1/aclk
    SLICE_X54Y75         SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[139].srl_nx1/shift_reg_reg[0]_srl32/CLK
                         clock pessimism              0.224     2.076    
    SLICE_X54Y75         SRLC32E (Hold_D6LUT_SLICEM_CLK_D)
                                                      0.046     2.122    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[139].srl_nx1/shift_reg_reg[0]_srl32
  -------------------------------------------------------------------
                         required time                         -2.122    
                         arrival time                           2.138    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][6][userdata][0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.706%)  route 0.111ns (65.294%))
  Logic Levels:           0  
  Clock Path Skew:        0.096ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.095ns
    Source Clock Delay      (SCD):    3.412ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Net Delay (Source):      1.653ns (routing 0.695ns, distribution 0.958ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.764ns, distribution 1.114ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.653     3.412    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X59Y66         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][6][userdata][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y66         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.471 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][6][userdata][0]/Q
                         net (fo=1, routed)           0.111     3.582    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/DIA1
    SLICE_X60Y66         RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.878     3.095    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/WCLK
    SLICE_X60Y66         RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1/CLK
                         clock pessimism              0.413     3.508    
    SLICE_X60Y66         RAMD32 (Hold_A6LUT_SLICEM_CLK_I)
                                                      0.058     3.566    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -3.566    
                         arrival time                           3.582    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][205]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_in_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAME_D1/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.058ns (31.351%)  route 0.127ns (68.649%))
  Logic Levels:           0  
  Clock Path Skew:        0.109ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.026ns
    Source Clock Delay      (SCD):    3.343ns
    Clock Pessimism Removal (CPR):    -0.426ns
  Clock Net Delay (Source):      1.584ns (routing 0.695ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.809ns (routing 0.764ns, distribution 1.045ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.584     3.343    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X66Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][205]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y99         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     3.401 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][205]/Q
                         net (fo=1, routed)           0.127     3.528    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_in_i/fifo_i/mem_i/RAM_reg_0_15_196_209/DIE1
    SLICE_X67Y97         RAMD32                                       r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_in_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAME_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.809     3.026    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_in_i/fifo_i/mem_i/RAM_reg_0_15_196_209/WCLK
    SLICE_X67Y97         RAMD32                                       r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_in_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAME_D1/CLK
                         clock pessimism              0.426     3.452    
    SLICE_X67Y97         RAMD32 (Hold_E6LUT_SLICEM_CLK_I)
                                                      0.060     3.512    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_in_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAME_D1
  -------------------------------------------------------------------
                         required time                         -3.512    
                         arrival time                           3.528    
  -------------------------------------------------------------------
                         slack                                  0.016    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin                    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     PS8/MAXIGP1ACLK            n/a            3.000         3.001       0.001      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y6   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y9   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y0              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y3              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y3              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y3              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y3              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y3              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y5  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y6  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y7  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y0               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y5  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y5  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.319      1.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y6  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.325      1.025      BITSLICE_CONTROL_X0Y5  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.326      1.026      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.326      1.026      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.327      1.027      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.327      1.027      BITSLICE_CONTROL_X0Y7  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.329      1.029      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.471      1.171      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.479      1.179      BITSLICE_CONTROL_X0Y6  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y6   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y9   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y11  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y14  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y15  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a            0.333         0.375       0.042      PLL_X0Y3                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y78  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y80  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y81  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y82  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y83  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack        9.924ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.015ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.469ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.924ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.882ns  (logic 0.380ns (20.192%)  route 1.502ns (79.808%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        -0.146ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.156ns = ( 15.159 - 12.002 ) 
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.660ns (routing 0.773ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.702ns, distribution 0.702ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.660     2.868    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X97Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y16         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.946 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/Q
                         net (fo=44, routed)          1.134     4.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[5]
    SLICE_X96Y10         LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.150     4.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_4/O
                         net (fo=1, routed)           0.048     4.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_4_n_0
    SLICE_X96Y10         LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     4.331 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_2/O
                         net (fo=1, routed)           0.248     4.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_2_n_0
    SLICE_X96Y10         LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.099     4.678 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_1/O
                         net (fo=1, routed)           0.072     4.750    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]
    SLICE_X96Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.404    15.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/C
                         clock pessimism             -0.434    14.725    
                         clock uncertainty           -0.076    14.649    
    SLICE_X96Y10         FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    14.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]
  -------------------------------------------------------------------
                         required time                         14.674    
                         arrival time                          -4.750    
  -------------------------------------------------------------------
                         slack                                  9.924    

Slack (MET) :             9.935ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.923ns  (logic 0.530ns (27.564%)  route 1.393ns (72.436%))
  Logic Levels:           4  (LUT3=1 LUT5=2 LUT6=1)
  Clock Path Skew:        -0.094ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.889ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.681ns (routing 0.773ns, distribution 0.908ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.681     2.889    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y11        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.968 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/Q
                         net (fo=7, routed)           0.271     3.239    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/Q[1]
    SLICE_X101Y13        LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     3.396 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/g0_b0__9_i_5/O
                         net (fo=1, routed)           0.357     3.753    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_2
    SLICE_X101Y13        LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     3.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_1/O
                         net (fo=22, routed)          0.543     4.385    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_1_n_0
    SLICE_X100Y12        LUT5 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.116     4.501 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__7/O
                         net (fo=1, routed)           0.173     4.674    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__7_n_0
    SLICE_X100Y12        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     4.763 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/dec_wdc_r_i_1/O
                         net (fo=1, routed)           0.048     4.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_10
    SLICE_X100Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.721    
    SLICE_X100Y12        FDCE (Setup_GFF_SLICEL_C_D)
                                                      0.025    14.746    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg
  -------------------------------------------------------------------
                         required time                         14.746    
                         arrival time                          -4.811    
  -------------------------------------------------------------------
                         slack                                  9.935    

Slack (MET) :             9.984ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.775ns  (logic 0.360ns (20.284%)  route 1.415ns (79.716%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.108ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.211ns = ( 15.214 - 12.002 ) 
    Source Clock Delay      (SCD):    2.889ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.681ns (routing 0.773ns, distribution 0.908ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.702ns, distribution 0.757ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.681     2.889    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y11        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.968 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/Q
                         net (fo=7, routed)           0.271     3.239    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/Q[1]
    SLICE_X101Y13        LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     3.396 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/g0_b0__9_i_5/O
                         net (fo=1, routed)           0.357     3.753    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_2
    SLICE_X101Y13        LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     3.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_1/O
                         net (fo=22, routed)          0.492     4.334    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_1_n_0
    SLICE_X100Y12        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     4.369 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.294     4.663    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X98Y13         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.459    15.214    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X98Y13         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/C
                         clock pessimism             -0.430    14.783    
                         clock uncertainty           -0.076    14.708    
    SLICE_X98Y13         FDCE (Setup_HFF_SLICEL_C_CE)
                                                     -0.060    14.648    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.648    
                         arrival time                          -4.663    
  -------------------------------------------------------------------
                         slack                                  9.984    

Slack (MET) :             10.017ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.845ns  (logic 0.524ns (28.405%)  route 1.321ns (71.595%))
  Logic Levels:           4  (LUT3=1 LUT5=2 LUT6=1)
  Clock Path Skew:        -0.090ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.229ns = ( 15.231 - 12.002 ) 
    Source Clock Delay      (SCD):    2.889ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.681ns (routing 0.773ns, distribution 0.908ns)
  Clock Net Delay (Destination): 1.476ns (routing 0.702ns, distribution 0.774ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.681     2.889    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y11        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.968 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/Q
                         net (fo=7, routed)           0.271     3.239    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/Q[1]
    SLICE_X101Y13        LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     3.396 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/g0_b0__9_i_5/O
                         net (fo=1, routed)           0.357     3.753    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_2
    SLICE_X101Y13        LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     3.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_1/O
                         net (fo=22, routed)          0.543     4.385    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_1_n_0
    SLICE_X100Y12        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.098     4.483 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__2/O
                         net (fo=1, routed)           0.091     4.574    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__2_n_0
    SLICE_X99Y12         LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     4.675 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/auto_sl_drdy_i_1/O
                         net (fo=1, routed)           0.058     4.733    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_8
    SLICE_X99Y12         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.476    15.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X99Y12         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                         clock pessimism             -0.430    14.801    
                         clock uncertainty           -0.076    14.725    
    SLICE_X99Y12         FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    14.750    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
  -------------------------------------------------------------------
                         required time                         14.750    
                         arrival time                          -4.733    
  -------------------------------------------------------------------
                         slack                                 10.017    

Slack (MET) :             10.022ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.847ns  (logic 0.532ns (28.810%)  route 1.315ns (71.190%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.877ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.670ns (routing 0.773ns, distribution 0.897ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.670     2.877    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y14        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y14        FDCE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/Q
                         net (fo=6, routed)           0.367     3.326    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[2]
    SLICE_X103Y11        LUT4 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.135     3.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.539     4.000    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X100Y13        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     4.097 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_3/O
                         net (fo=23, routed)          0.225     4.322    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_3_n_0
    SLICE_X101Y14        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.123     4.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__8/O
                         net (fo=1, routed)           0.133     4.578    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__8_n_0
    SLICE_X102Y12        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     4.674 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_den_r[0]_i_1/O
                         net (fo=1, routed)           0.050     4.724    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_12
    SLICE_X102Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.721    
    SLICE_X102Y12        FDCE (Setup_CFF_SLICEL_C_D)
                                                      0.025    14.746    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.746    
                         arrival time                          -4.724    
  -------------------------------------------------------------------
                         slack                                 10.022    

Slack (MET) :             10.075ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.795ns  (logic 0.500ns (27.861%)  route 1.295ns (72.139%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.226ns = ( 15.228 - 12.002 ) 
    Source Clock Delay      (SCD):    2.877ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.670ns (routing 0.773ns, distribution 0.897ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.702ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.670     2.877    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y14        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y14        FDCE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/Q
                         net (fo=6, routed)           0.367     3.326    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[2]
    SLICE_X103Y11        LUT4 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.135     3.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.539     4.000    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X100Y13        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     4.097 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_3/O
                         net (fo=23, routed)          0.225     4.322    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_3_n_0
    SLICE_X101Y14        LUT5 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.136     4.458 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9/O
                         net (fo=1, routed)           0.112     4.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_n_0
    SLICE_X101Y13        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     4.621 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_dwe_r[0]_i_1/O
                         net (fo=1, routed)           0.051     4.672    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_13
    SLICE_X101Y13        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473    15.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y13        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/C
                         clock pessimism             -0.430    14.798    
                         clock uncertainty           -0.076    14.722    
    SLICE_X101Y13        FDCE (Setup_HFF_SLICEL_C_D)
                                                      0.025    14.747    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.747    
                         arrival time                          -4.672    
  -------------------------------------------------------------------
                         slack                                 10.075    

Slack (MET) :             10.090ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.863ns  (logic 0.527ns (28.289%)  route 1.336ns (71.711%))
  Logic Levels:           5  (LUT2=1 LUT3=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.001ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.790ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.582ns (routing 0.773ns, distribution 0.809ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.582     2.790    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X96Y12         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y12         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.866 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.399     3.264    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X102Y11        LUT2 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.089     3.353 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state[14]_i_2/O
                         net (fo=6, routed)           0.261     3.614    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg
    SLICE_X100Y11        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     3.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_9/O
                         net (fo=2, routed)           0.199     3.864    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_9_n_0
    SLICE_X101Y12        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     3.988 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.275     4.263    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X101Y13        LUT5 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.136     4.399 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__5/O
                         net (fo=1, routed)           0.157     4.556    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__5_n_0
    SLICE_X100Y12        LUT3 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     4.607 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/inc_addr_r_i_1/O
                         net (fo=1, routed)           0.046     4.653    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_9
    SLICE_X100Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/C
                         clock pessimism             -0.434    14.793    
                         clock uncertainty           -0.076    14.718    
    SLICE_X100Y12        FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.025    14.743    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg
  -------------------------------------------------------------------
                         required time                         14.743    
                         arrival time                          -4.653    
  -------------------------------------------------------------------
                         slack                                 10.090    

Slack (MET) :             10.106ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.702ns  (logic 0.327ns (19.210%)  route 1.375ns (80.790%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        -0.144ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.158ns = ( 15.160 - 12.002 ) 
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.660ns (routing 0.773ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.702ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.660     2.868    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X97Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y16         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.946 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/Q
                         net (fo=44, routed)          1.027     3.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[5]
    SLICE_X96Y6          LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     4.063 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[1]_i_4/O
                         net (fo=1, routed)           0.147     4.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[1]_i_4_n_0
    SLICE_X95Y7          LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     4.334 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[1]_i_2/O
                         net (fo=1, routed)           0.151     4.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[1]_i_2_n_0
    SLICE_X95Y9          LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     4.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[1]_i_1/O
                         net (fo=1, routed)           0.050     4.570    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[1]
    SLICE_X95Y9          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.405    15.160    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y9          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[1]/C
                         clock pessimism             -0.434    14.726    
                         clock uncertainty           -0.076    14.651    
    SLICE_X95Y9          FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025    14.676    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[1]
  -------------------------------------------------------------------
                         required time                         14.676    
                         arrival time                          -4.570    
  -------------------------------------------------------------------
                         slack                                 10.106    

Slack (MET) :             10.113ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.739ns  (logic 0.659ns (37.889%)  route 1.080ns (62.111%))
  Logic Levels:           5  (LUT2=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.226ns = ( 15.228 - 12.002 ) 
    Source Clock Delay      (SCD):    2.895ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.687ns (routing 0.773ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.702ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.687     2.895    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X99Y12         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y12         FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/Q
                         net (fo=12, routed)          0.266     3.240    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy
    SLICE_X102Y11        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     3.362 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state[14]_i_2/O
                         net (fo=6, routed)           0.261     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg
    SLICE_X100Y11        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     3.673 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_9/O
                         net (fo=2, routed)           0.199     3.872    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_9_n_0
    SLICE_X101Y12        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     3.996 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.275     4.271    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X101Y13        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.123     4.394 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b1/O
                         net (fo=1, routed)           0.064     4.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_16
    SLICE_X101Y13        LUT4 (Prop_G5LUT_SLICEL_I2_O)
                                                      0.160     4.618 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1/O
                         net (fo=1, routed)           0.016     4.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1_n_0
    SLICE_X101Y13        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473    15.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y13        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/C
                         clock pessimism             -0.430    14.798    
                         clock uncertainty           -0.076    14.722    
    SLICE_X101Y13        FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    14.747    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]
  -------------------------------------------------------------------
                         required time                         14.747    
                         arrival time                          -4.634    
  -------------------------------------------------------------------
                         slack                                 10.113    

Slack (MET) :             10.138ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.733ns  (logic 0.348ns (20.087%)  route 1.385ns (79.913%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.227ns = ( 15.229 - 12.002 ) 
    Source Clock Delay      (SCD):    2.877ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.670ns (routing 0.773ns, distribution 0.897ns)
  Clock Net Delay (Destination): 1.474ns (routing 0.702ns, distribution 0.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.670     2.877    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X100Y14        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y14        FDCE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.958 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/Q
                         net (fo=6, routed)           0.367     3.326    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[2]
    SLICE_X103Y11        LUT4 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.135     3.461 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.539     4.000    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X100Y13        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     4.097 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_3/O
                         net (fo=23, routed)          0.430     4.527    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_3_n_0
    SLICE_X101Y12        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     4.562 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_berr_r[0]_i_1/O
                         net (fo=1, routed)           0.048     4.610    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_5
    SLICE_X101Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.474    15.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y12        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/C
                         clock pessimism             -0.430    14.799    
                         clock uncertainty           -0.076    14.723    
    SLICE_X101Y12        FDCE (Setup_GFF_SLICEL_C_D)
                                                      0.025    14.748    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.748    
                         arrival time                          -4.610    
  -------------------------------------------------------------------
                         slack                                 10.138    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.080ns (47.357%)  route 0.089ns (52.643%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.889ns
    Source Clock Delay      (SCD):    3.225ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Net Delay (Source):      1.473ns (routing 0.702ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.681ns (routing 0.773ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473     3.225    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y11        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     3.283 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]/Q
                         net (fo=2, routed)           0.065     3.348    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/Q[16]
    SLICE_X102Y11        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.022     3.370 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state[14]_i_1/O
                         net (fo=1, routed)           0.024     3.394    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_21
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.681     2.889    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                         clock pessimism              0.430     3.319    
    SLICE_X102Y11        FDCE (Hold_CFF_SLICEL_C_D)
                                                      0.060     3.379    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]
  -------------------------------------------------------------------
                         required time                         -3.379    
                         arrival time                           3.394    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.060ns (44.118%)  route 0.076ns (55.882%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.822ns
    Source Clock Delay      (SCD):    3.159ns
    Clock Pessimism Removal (CPR):    -0.388ns
  Clock Net Delay (Source):      1.406ns (routing 0.702ns, distribution 0.704ns)
  Clock Net Delay (Destination): 1.614ns (routing 0.773ns, distribution 0.841ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.406     3.159    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X95Y5          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y5          FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.219 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/Q
                         net (fo=2, routed)           0.076     3.295    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[29]
    SLICE_X95Y6          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.614     2.822    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y6          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[8]/C
                         clock pessimism              0.388     3.210    
    SLICE_X95Y6          FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     3.270    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.270    
                         arrival time                           3.295    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.080ns  (logic 0.039ns (48.843%)  route 0.041ns (51.157%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.656ns
    Source Clock Delay      (SCD):    1.876ns
    Clock Pessimism Removal (CPR):    -0.227ns
  Clock Net Delay (Source):      0.877ns (routing 0.426ns, distribution 0.451ns)
  Clock Net Delay (Destination): 0.999ns (routing 0.477ns, distribution 0.522ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.877     1.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y8          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y8          FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/Q
                         net (fo=2, routed)           0.041     1.956    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[7]
    SLICE_X95Y8          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.999     1.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y8          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
                         clock pessimism              0.227     1.882    
    SLICE_X95Y8          FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.046     1.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.928    
                         arrival time                           1.956    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.669ns
    Source Clock Delay      (SCD):    1.888ns
    Clock Pessimism Removal (CPR):    -0.225ns
  Clock Net Delay (Source):      0.889ns (routing 0.426ns, distribution 0.463ns)
  Clock Net Delay (Destination): 1.013ns (routing 0.477ns, distribution 0.536ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.889     1.888    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y4          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y4          FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/Q
                         net (fo=2, routed)           0.043     1.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[33]
    SLICE_X95Y4          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.013     1.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y4          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]/C
                         clock pessimism              0.225     1.894    
    SLICE_X95Y4          FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.940    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[33]
  -------------------------------------------------------------------
                         required time                         -1.940    
                         arrival time                           1.970    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.935%)  route 0.044ns (53.065%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.672ns
    Source Clock Delay      (SCD):    1.890ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.891ns (routing 0.426ns, distribution 0.465ns)
  Clock Net Delay (Destination): 1.016ns (routing 0.477ns, distribution 0.539ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.891     1.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y4          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y4          FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.929 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]/Q
                         net (fo=2, routed)           0.044     1.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[84]
    SLICE_X94Y4          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.016     1.672    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y4          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]/C
                         clock pessimism              0.224     1.896    
    SLICE_X94Y4          FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     1.942    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[84]
  -------------------------------------------------------------------
                         required time                         -1.942    
                         arrival time                           1.973    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.258ns  (logic 0.057ns (22.122%)  route 0.201ns (77.878%))
  Logic Levels:           0  
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.893ns
    Source Clock Delay      (SCD):    3.157ns
    Clock Pessimism Removal (CPR):    -0.434ns
  Clock Net Delay (Source):      1.405ns (routing 0.702ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.685ns (routing 0.773ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.405     3.157    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X96Y4          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y4          FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     3.214 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[14]/Q
                         net (fo=2, routed)           0.201     3.415    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/D
    SLICE_X97Y9          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.685     2.893    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/WCLK
    SLICE_X97Y9          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP/CLK
                         clock pessimism              0.434     3.327    
    SLICE_X97Y9          RAMD32 (Hold_H6LUT_SLICEM_CLK_I)
                                                      0.056     3.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP
  -------------------------------------------------------------------
                         required time                         -3.383    
                         arrival time                           3.415    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk_r1_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.040ns (40.404%)  route 0.059ns (59.596%))
  Logic Levels:           0  
  Clock Path Skew:        0.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.668ns
    Source Clock Delay      (SCD):    1.882ns
    Clock Pessimism Removal (CPR):    -0.233ns
  Clock Net Delay (Source):      0.882ns (routing 0.426ns, distribution 0.456ns)
  Clock Net Delay (Destination): 1.011ns (routing 0.477ns, distribution 0.534ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.882     1.882    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y2          FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.922 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[1]/Q
                         net (fo=1, routed)           0.059     1.981    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk
    SLICE_X94Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk_r1_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.011     1.668    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk_r1_reg/C
                         clock pessimism              0.233     1.901    
    SLICE_X94Y2          FDRE (Hold_GFF2_SLICEM_C_D)
                                                      0.047     1.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_sclk_r1_reg
  -------------------------------------------------------------------
                         required time                         -1.948    
                         arrival time                           1.981    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.341%)  route 0.065ns (62.659%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.663ns
    Source Clock Delay      (SCD):    1.884ns
    Clock Pessimism Removal (CPR):    -0.241ns
  Clock Net Delay (Source):      0.885ns (routing 0.426ns, distribution 0.459ns)
  Clock Net Delay (Destination): 1.006ns (routing 0.477ns, distribution 0.529ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.885     1.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y7          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y7          FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.923 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/Q
                         net (fo=2, routed)           0.065     1.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[28]
    SLICE_X96Y8          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.006     1.663    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y8          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[7]/C
                         clock pessimism              0.241     1.904    
    SLICE_X96Y8          FDRE (Hold_GFF2_SLICEM_C_D)
                                                      0.047     1.951    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.951    
                         arrival time                           1.988    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.037ns (41.111%)  route 0.053ns (58.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.660ns
    Source Clock Delay      (SCD):    1.880ns
    Clock Pessimism Removal (CPR):    -0.227ns
  Clock Net Delay (Source):      0.881ns (routing 0.426ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.003ns (routing 0.477ns, distribution 0.526ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.881     1.880    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y3          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y3          FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]/Q
                         net (fo=2, routed)           0.053     1.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[78]
    SLICE_X96Y3          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.003     1.660    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y3          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]/C
                         clock pessimism              0.227     1.886    
    SLICE_X96Y3          FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     1.932    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[78]
  -------------------------------------------------------------------
                         required time                         -1.932    
                         arrival time                           1.970    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.212ns  (logic 0.060ns (28.302%)  route 0.152ns (71.698%))
  Logic Levels:           0  
  Clock Path Skew:        0.095ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.824ns
    Source Clock Delay      (SCD):    3.165ns
    Clock Pessimism Removal (CPR):    -0.436ns
  Clock Net Delay (Source):      1.412ns (routing 0.702ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.616ns (routing 0.773ns, distribution 0.843ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.412     3.165    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X94Y6          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y6          FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.060     3.225 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[2]/Q
                         net (fo=1, routed)           0.152     3.377    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/DIB0
    SLICE_X96Y9          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.616     2.824    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X96Y9          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
                         clock pessimism              0.436     3.260    
    SLICE_X96Y9          RAMD32 (Hold_B5LUT_SLICEM_CLK_I)
                                                      0.078     3.338    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -3.338    
                         arrival time                           3.377    
  -------------------------------------------------------------------
                         slack                                  0.039    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout5
Waveform(ns):       { 0.000 6.001 }
Period(ns):         12.002
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     BUFGCE/I            n/a            1.290         12.002      10.712     BUFGCE_X0Y41  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/I
Min Period        n/a     MMCME4_ADV/CLKOUT5  n/a            1.071         12.002      10.931     MMCM_X0Y1     d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X96Y9   dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.496ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.023ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.009ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.496ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.066ns  (logic 0.525ns (12.911%)  route 3.541ns (87.089%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.244ns = ( 9.245 - 6.001 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.764ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.695ns, distribution 0.778ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.612     2.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X89Y100        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y100        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     3.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X89Y100        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.096 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.852     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X87Y80         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     4.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.981     5.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X85Y109        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.277     5.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X86Y102        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.300     6.912    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X8Y13         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.473     9.245    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y13         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.818    
                         clock uncertainty           -0.068     8.750    
    RAMB36_X8Y13         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.408    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.408    
                         arrival time                          -6.912    
  -------------------------------------------------------------------
                         slack                                  1.496    

Slack (MET) :             1.521ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.043ns  (logic 0.525ns (12.984%)  route 3.518ns (87.016%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.246ns = ( 9.247 - 6.001 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.764ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.475ns (routing 0.695ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.612     2.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X89Y100        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y100        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     3.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X89Y100        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.096 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.852     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X87Y80         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     4.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.981     5.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X85Y109        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.277     5.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X86Y102        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.277     6.889    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.475     9.247    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.820    
                         clock uncertainty           -0.068     8.752    
    RAMB36_X8Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.410    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.410    
                         arrival time                          -6.889    
  -------------------------------------------------------------------
                         slack                                  1.521    

Slack (MET) :             1.554ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.009ns  (logic 0.556ns (13.868%)  route 3.453ns (86.132%))
  Logic Levels:           3  (CARRY8=1 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.246ns = ( 9.247 - 6.001 ) 
    Source Clock Delay      (SCD):    2.855ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.621ns (routing 0.764ns, distribution 0.857ns)
  Clock Net Delay (Destination): 1.475ns (routing 0.695ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.621     2.855    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X89Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y114        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/Q
                         net (fo=65, routed)          0.843     3.776    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I1
    SLICE_X90Y107        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.123     3.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.021     3.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_6
    SLICE_X90Y107        CARRY8 (Prop_CARRY8_SLICEM_S[2]_O[5])
                                                      0.207     4.127 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/O[5]
                         net (fo=27, routed)          0.758     4.885    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[2]
    SLICE_X86Y109        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     5.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[27]_INST_0/O
                         net (fo=25, routed)          1.831     6.864    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/addrb[2]
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.475     9.247    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.820    
                         clock uncertainty           -0.068     8.752    
    RAMB36_X8Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[3])
                                                     -0.334     8.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.418    
                         arrival time                          -6.864    
  -------------------------------------------------------------------
                         slack                                  1.554    

Slack (MET) :             1.629ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.934ns  (logic 0.525ns (13.345%)  route 3.409ns (86.655%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.245ns = ( 9.246 - 6.001 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.764ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.695ns, distribution 0.778ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.612     2.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X89Y100        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y100        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     3.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X89Y100        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.096 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.852     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X87Y80         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     4.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.981     5.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X85Y109        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.277     5.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X86Y102        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.167     6.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X9Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.473     9.246    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.819    
                         clock uncertainty           -0.068     8.750    
    RAMB36_X9Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.408    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.408    
                         arrival time                          -6.780    
  -------------------------------------------------------------------
                         slack                                  1.629    

Slack (MET) :             1.647ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.912ns  (logic 0.525ns (13.422%)  route 3.387ns (86.578%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.241ns = ( 9.242 - 6.001 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.764ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.469ns (routing 0.695ns, distribution 0.774ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.612     2.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X89Y100        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y100        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     3.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X89Y100        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.096 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.852     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X87Y80         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     4.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.981     5.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X85Y109        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.277     5.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X86Y102        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.145     6.757    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X9Y23         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.469     9.242    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y23         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.815    
                         clock uncertainty           -0.068     8.746    
    RAMB36_X9Y23         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.404    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.404    
                         arrival time                          -6.757    
  -------------------------------------------------------------------
                         slack                                  1.647    

Slack (MET) :             1.668ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.893ns  (logic 0.556ns (14.284%)  route 3.337ns (85.716%))
  Logic Levels:           3  (CARRY8=1 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.244ns = ( 9.245 - 6.001 ) 
    Source Clock Delay      (SCD):    2.855ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.621ns (routing 0.764ns, distribution 0.857ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.695ns, distribution 0.778ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.621     2.855    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X89Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y114        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/Q
                         net (fo=65, routed)          0.843     3.776    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I1
    SLICE_X90Y107        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.123     3.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.021     3.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_6
    SLICE_X90Y107        CARRY8 (Prop_CARRY8_SLICEM_S[2]_O[5])
                                                      0.207     4.127 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/O[5]
                         net (fo=27, routed)          0.758     4.885    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[2]
    SLICE_X86Y109        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     5.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[27]_INST_0/O
                         net (fo=25, routed)          1.715     6.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/addrb[2]
    RAMB36_X8Y13         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.473     9.245    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y13         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.818    
                         clock uncertainty           -0.068     8.750    
    RAMB36_X8Y13         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[3])
                                                     -0.334     8.416    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.416    
                         arrival time                          -6.747    
  -------------------------------------------------------------------
                         slack                                  1.668    

Slack (MET) :             1.720ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[4]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.831ns  (logic 0.556ns (14.515%)  route 3.275ns (85.485%))
  Logic Levels:           3  (CARRY8=1 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.242ns = ( 9.243 - 6.001 ) 
    Source Clock Delay      (SCD):    2.855ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.621ns (routing 0.764ns, distribution 0.857ns)
  Clock Net Delay (Destination): 1.471ns (routing 0.695ns, distribution 0.776ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.621     2.855    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X89Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y114        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/Q
                         net (fo=65, routed)          0.843     3.776    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I1
    SLICE_X90Y107        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.123     3.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.021     3.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_6
    SLICE_X90Y107        CARRY8 (Prop_CARRY8_SLICEM_S[2]_O[5])
                                                      0.207     4.127 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/O[5]
                         net (fo=27, routed)          0.758     4.885    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[2]
    SLICE_X86Y109        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     5.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[27]_INST_0/O
                         net (fo=25, routed)          1.653     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/addrb[2]
    RAMB36_X8Y14         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.471     9.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y14         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.816    
                         clock uncertainty           -0.068     8.748    
    RAMB36_X8Y14         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[4])
                                                     -0.343     8.405    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.405    
                         arrival time                          -6.685    
  -------------------------------------------------------------------
                         slack                                  1.720    

Slack (MET) :             1.724ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.888ns  (logic 0.606ns (15.587%)  route 3.282ns (84.413%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.246ns = ( 9.247 - 6.001 ) 
    Source Clock Delay      (SCD):    2.855ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.621ns (routing 0.764ns, distribution 0.857ns)
  Clock Net Delay (Destination): 1.475ns (routing 0.695ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.621     2.855    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X89Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y114        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_ALU_Op_reg[0]/Q
                         net (fo=65, routed)          0.843     3.776    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I1
    SLICE_X90Y107        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.123     3.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[30].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.021     3.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_6
    SLICE_X90Y107        CARRY8 (Prop_CARRY8_SLICEM_S[2]_CO[7])
                                                      0.161     4.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.107    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X90Y108        CARRY8 (Prop_CARRY8_SLICEM_CI_O[1])
                                                      0.083     4.190 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[1]
                         net (fo=27, routed)          0.721     4.911    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[6]
    SLICE_X85Y109        LUT3 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.161     5.072 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[23]_INST_0/O
                         net (fo=25, routed)          1.670     6.743    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/addrb[6]
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.475     9.247    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y12         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.820    
                         clock uncertainty           -0.068     8.752    
    RAMB36_X8Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[7])
                                                     -0.285     8.467    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.467    
                         arrival time                          -6.743    
  -------------------------------------------------------------------
                         slack                                  1.724    

Slack (MET) :             1.729ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.822ns  (logic 0.525ns (13.736%)  route 3.297ns (86.264%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.233ns = ( 9.234 - 6.001 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.764ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.462ns (routing 0.695ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.612     2.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X89Y100        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y100        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     3.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X89Y100        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.096 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.852     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X87Y80         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     4.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.981     5.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X85Y109        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.277     5.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X86Y102        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.055     6.668    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X8Y16         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.462     9.234    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y16         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.807    
                         clock uncertainty           -0.068     8.739    
    RAMB36_X8Y16         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.397    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.397    
                         arrival time                          -6.668    
  -------------------------------------------------------------------
                         slack                                  1.729    

Slack (MET) :             1.752ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.805ns  (logic 0.525ns (13.799%)  route 3.280ns (86.201%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.239ns = ( 9.240 - 6.001 ) 
    Source Clock Delay      (SCD):    2.846ns
    Clock Pessimism Removal (CPR):    -0.427ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.764ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.468ns (routing 0.695ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.612     2.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X89Y100        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y100        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.Sl_Rdy_reg/Q
                         net (fo=1, routed)           0.131     3.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Rdy
    SLICE_X89Y100        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.096 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.852     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X87Y80         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     4.109 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.981     5.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X85Y109        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.277     5.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X86Y102        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.038     6.650    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X9Y13         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.468     9.240    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y13         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.427     8.813    
                         clock uncertainty           -0.068     8.745    
    RAMB36_X9Y13         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.403    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.403    
                         arrival time                          -6.650    
  -------------------------------------------------------------------
                         slack                                  1.752    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[27]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][27]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.455%)  route 0.065ns (62.546%))
  Logic Levels:           0  
  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    1.919ns
    Clock Pessimism Removal (CPR):    -0.239ns
  Clock Net Delay (Source):      0.904ns (routing 0.421ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.041ns (routing 0.473ns, distribution 0.568ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.904     1.919    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X87Y106        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y106        FDSE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.958 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[27]/Q
                         net (fo=4, routed)           0.065     2.023    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/S17_in
    SLICE_X87Y107        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][27]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.041     1.715    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X87Y107        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][27]_srl4/CLK
                         clock pessimism              0.239     1.954    
    SLICE_X87Y107        SRL16E (Hold_D5LUT_SLICEM_CLK_D)
                                                      0.046     2.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][27]_srl4
  -------------------------------------------------------------------
                         required time                         -2.000    
                         arrival time                           2.023    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.027ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.278ns  (logic 0.058ns (20.863%)  route 0.220ns (79.137%))
  Logic Levels:           0  
  Clock Path Skew:        0.191ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.881ns
    Source Clock Delay      (SCD):    3.158ns
    Clock Pessimism Removal (CPR):    -0.469ns
  Clock Net Delay (Source):      1.387ns (routing 0.695ns, distribution 0.692ns)
  Clock Net Delay (Destination): 1.647ns (routing 0.764ns, distribution 0.883ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.387     3.158    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y55         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y55         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.216 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[23]/Q
                         net (fo=1, routed)           0.220     3.436    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[23]
    SLICE_X92Y71         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.647     2.881    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X92Y71         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[23]/C
                         clock pessimism              0.469     3.349    
    SLICE_X92Y71         FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.409    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[23]
  -------------------------------------------------------------------
                         required time                         -3.409    
                         arrival time                           3.436    
  -------------------------------------------------------------------
                         slack                                  0.027    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.mem_mask1_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.081ns (47.430%)  route 0.090ns (52.570%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.859ns
    Source Clock Delay      (SCD):    3.206ns
    Clock Pessimism Removal (CPR):    -0.429ns
  Clock Net Delay (Source):      1.434ns (routing 0.695ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.625ns (routing 0.764ns, distribution 0.861ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.434     3.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X92Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y111        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.265 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[21]/Q
                         net (fo=46, routed)          0.061     3.325    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[0]_0[10]
    SLICE_X93Y111        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.022     3.347 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Use_HW_BS.Using_BitField.mem_mask1[29]_i_1/O
                         net (fo=1, routed)           0.029     3.376    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.mem_mask1_reg[0]_0[1]
    SLICE_X93Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.mem_mask1_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.625     2.859    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Clk
    SLICE_X93Y111        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.mem_mask1_reg[29]/C
                         clock pessimism              0.429     3.288    
    SLICE_X93Y111        FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.060     3.348    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.mem_mask1_reg[29]
  -------------------------------------------------------------------
                         required time                         -3.348    
                         arrival time                           3.376    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[25]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][25]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.202ns  (logic 0.060ns (29.649%)  route 0.142ns (70.351%))
  Logic Levels:           0  
  Clock Path Skew:        0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.879ns
    Source Clock Delay      (SCD):    3.197ns
    Clock Pessimism Removal (CPR):    -0.429ns
  Clock Net Delay (Source):      1.426ns (routing 0.695ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.645ns (routing 0.764ns, distribution 0.881ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.426     3.197    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X89Y107        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y107        FDSE (Prop_GFF2_SLICEM_C_Q)
                                                      0.060     3.257 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[25]/Q
                         net (fo=4, routed)           0.142     3.399    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/S27_in
    SLICE_X87Y107        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][25]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.645     2.879    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X87Y107        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][25]_srl4/CLK
                         clock pessimism              0.429     3.308    
    SLICE_X87Y107        SRL16E (Hold_B5LUT_SLICEM_CLK_D)
                                                      0.055     3.363    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][25]_srl4
  -------------------------------------------------------------------
                         required time                         -3.363    
                         arrival time                           3.399    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_read_data_reg[50]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.267ns  (logic 0.101ns (37.828%)  route 0.166ns (62.172%))
  Logic Levels:           2  (LUT6=1 MUXF7=1)
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.876ns
    Source Clock Delay      (SCD):    3.175ns
    Clock Pessimism Removal (CPR):    -0.469ns
  Clock Net Delay (Source):      1.404ns (routing 0.695ns, distribution 0.709ns)
  Clock Net Delay (Destination): 1.642ns (routing 0.764ns, distribution 0.878ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.404     3.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y55         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_read_data_reg[50]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y55         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     3.235 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_read_data_reg[50]/Q
                         net (fo=1, routed)           0.146     3.381    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_read_data[50]
    SLICE_X81Y63         LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.022     3.403 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_3/O
                         net (fo=1, routed)           0.010     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_3_n_0
    SLICE_X81Y63         MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.019     3.432 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1/O
                         net (fo=1, routed)           0.010     3.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1_n_0
    SLICE_X81Y63         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.642     2.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y63         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/C
                         clock pessimism              0.469     3.344    
    SLICE_X81Y63         FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     3.404    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.404    
                         arrival time                           3.442    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[22].mem_Rd_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.128ns  (logic 0.038ns (29.666%)  route 0.090ns (70.334%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    1.914ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.899ns (routing 0.421ns, distribution 0.478ns)
  Clock Net Delay (Destination): 1.017ns (routing 0.473ns, distribution 0.544ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.899     1.914    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X93Y106        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y106        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.952 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[22]/Q
                         net (fo=3, routed)           0.090     2.042    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Q[9]
    SLICE_X95Y106        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[22].mem_Rd_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.017     1.691    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Clk
    SLICE_X95Y106        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[22].mem_Rd_reg[22]/C
                         clock pessimism              0.266     1.956    
    SLICE_X95Y106        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.047     2.003    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[22].mem_Rd_reg[22]
  -------------------------------------------------------------------
                         required time                         -2.003    
                         arrival time                           2.042    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.059ns (64.172%)  route 0.033ns (35.828%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    1.912ns
    Clock Pessimism Removal (CPR):    -0.225ns
  Clock Net Delay (Source):      0.897ns (routing 0.421ns, distribution 0.476ns)
  Clock Net Delay (Destination): 1.019ns (routing 0.473ns, distribution 0.546ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.897     1.912    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y102        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.951 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.027     1.978    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X95Y102        LUT5 (Prop_G5LUT_SLICEL_I2_O)
                                                      0.020     1.998 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int[4]_i_1/O
                         net (fo=1, routed)           0.006     2.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int0[4]
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.019     1.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/C
                         clock pessimism              0.225     1.918    
    SLICE_X95Y102        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.047     1.965    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.965    
                         arrival time                           2.004    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_div_instr_I_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.135ns  (logic 0.058ns (43.021%)  route 0.077ns (56.979%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.868ns
    Source Clock Delay      (SCD):    3.206ns
    Clock Pessimism Removal (CPR):    -0.371ns
  Clock Net Delay (Source):      1.434ns (routing 0.695ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.634ns (routing 0.764ns, distribution 0.870ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.434     3.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X88Y117        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_div_instr_I_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y117        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.264 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_div_instr_I_reg/Q
                         net (fo=4, routed)           0.077     3.341    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Is_Div_Instr
    SLICE_X88Y117        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.634     2.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X88Y117        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg/C
                         clock pessimism              0.371     3.239    
    SLICE_X88Y117        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.301    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg
  -------------------------------------------------------------------
                         required time                         -3.301    
                         arrival time                           3.341    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/core_dec_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg/D
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.062ns (45.255%)  route 0.075ns (54.745%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.694ns
    Source Clock Delay      (SCD):    1.908ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.893ns (routing 0.421ns, distribution 0.472ns)
  Clock Net Delay (Destination): 1.020ns (routing 0.473ns, distribution 0.547ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.893     1.908    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/slowest_sync_clk
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/core_dec_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y103        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.948 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/core_dec_reg[2]/Q
                         net (fo=1, routed)           0.049     1.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/p_0_in
    SLICE_X96Y103        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.022     2.019 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_i_1/O
                         net (fo=1, routed)           0.026     2.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_i_1_n_0
    SLICE_X96Y103        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.020     1.694    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/slowest_sync_clk
    SLICE_X96Y103        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg/C
                         clock pessimism              0.266     1.960    
    SLICE_X96Y103        FDSE (Hold_DFF_SLICEM_C_D)
                                                      0.046     2.006    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg
  -------------------------------------------------------------------
                         required time                         -2.006    
                         arrival time                           2.045    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[17].mem_Rd_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.200ns  (logic 0.059ns (29.441%)  route 0.141ns (70.560%))
  Logic Levels:           0  
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.869ns
    Source Clock Delay      (SCD):    3.198ns
    Clock Pessimism Removal (CPR):    -0.429ns
  Clock Net Delay (Source):      1.427ns (routing 0.695ns, distribution 0.732ns)
  Clock Net Delay (Destination): 1.635ns (routing 0.764ns, distribution 0.871ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.427     3.198    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X92Y107        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y107        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.257 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[17]/Q
                         net (fo=3, routed)           0.141     3.398    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Q[14]
    SLICE_X94Y107        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[17].mem_Rd_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.635     2.869    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Clk
    SLICE_X94Y107        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[17].mem_Rd_reg[17]/C
                         clock pessimism              0.429     3.298    
    SLICE_X94Y107        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.060     3.358    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[17].mem_Rd_reg[17]
  -------------------------------------------------------------------
                         required time                         -3.358    
                         arrival time                           3.398    
  -------------------------------------------------------------------
                         slack                                  0.041    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 3.001 }
Period(ns):         6.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y6   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y7   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.809       1.009      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.809       1.009      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.806       1.012      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.806       1.012      BITSLICE_CONTROL_X0Y7   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.804       1.014      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.804       1.014      BITSLICE_CONTROL_X0Y5   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.803       1.015      BITSLICE_CONTROL_X0Y6   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.799       1.019      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Slow    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.440       1.378      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Slow    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.436       1.382      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.618ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.618ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.409ns  (logic 0.081ns (19.804%)  route 0.328ns (80.196%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y4                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X98Y4          FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.328     0.409    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X98Y3          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X98Y3          FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.409    
  -------------------------------------------------------------------
                         slack                                 11.618    

Slack (MET) :             11.691ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.336ns  (logic 0.076ns (22.619%)  route 0.260ns (77.381%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y4                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X99Y4          FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.260     0.336    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X98Y3          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X98Y3          FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.336    
  -------------------------------------------------------------------
                         slack                                 11.691    

Slack (MET) :             11.735ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.292ns  (logic 0.077ns (26.370%)  route 0.215ns (73.630%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y5                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X99Y5          FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     0.077 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.215     0.292    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X98Y3          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X98Y3          FDCE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.292    
  -------------------------------------------------------------------
                         slack                                 11.735    

Slack (MET) :             11.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.283ns  (logic 0.079ns (27.915%)  route 0.204ns (72.085%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y4                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X100Y4         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.204     0.283    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y4         FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.283    
  -------------------------------------------------------------------
                         slack                                 11.744    

Slack (MET) :             11.745ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.282ns  (logic 0.077ns (27.305%)  route 0.205ns (72.695%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y8                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X99Y8          FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     0.077 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.205     0.282    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X99Y8          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X99Y8          FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.282    
  -------------------------------------------------------------------
                         slack                                 11.745    

Slack (MET) :             11.753ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.274ns  (logic 0.079ns (28.832%)  route 0.195ns (71.168%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X100Y9         FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.195     0.274    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y9         FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.274    
  -------------------------------------------------------------------
                         slack                                 11.753    

Slack (MET) :             11.797ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.230ns  (logic 0.080ns (34.783%)  route 0.150ns (65.217%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X100Y9         FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.150     0.230    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X100Y8         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y8         FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.230    
  -------------------------------------------------------------------
                         slack                                 11.797    

Slack (MET) :             11.798ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.229ns  (logic 0.079ns (34.498%)  route 0.150ns (65.502%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X100Y9         FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.150     0.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X100Y8         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X100Y8         FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.229    
  -------------------------------------------------------------------
                         slack                                 11.798    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        2.508ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.508ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.517ns  (logic 0.079ns (15.280%)  route 0.438ns (84.720%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y20                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
    SLICE_X96Y20         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/Q
                         net (fo=1, routed)           0.438     0.517    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[5]
    SLICE_X92Y21         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y21         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.517    
  -------------------------------------------------------------------
                         slack                                  2.508    

Slack (MET) :             2.552ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.473ns  (logic 0.079ns (16.702%)  route 0.394ns (83.298%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y9                                       0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
    SLICE_X95Y9          FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/Q
                         net (fo=1, routed)           0.394     0.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[1]
    SLICE_X93Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y10         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.473    
  -------------------------------------------------------------------
                         slack                                  2.552    

Slack (MET) :             2.564ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.461ns  (logic 0.078ns (16.920%)  route 0.383ns (83.080%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y24                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
    SLICE_X96Y24         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/Q
                         net (fo=1, routed)           0.383     0.461    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[10]
    SLICE_X96Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X96Y26         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.461    
  -------------------------------------------------------------------
                         slack                                  2.564    

Slack (MET) :             2.572ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.453ns  (logic 0.078ns (17.219%)  route 0.375ns (82.781%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y7                                       0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
    SLICE_X94Y7          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/Q
                         net (fo=1, routed)           0.375     0.453    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[3]
    SLICE_X94Y21         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y21         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.453    
  -------------------------------------------------------------------
                         slack                                  2.572    

Slack (MET) :             2.596ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.429ns  (logic 0.078ns (18.182%)  route 0.351ns (81.818%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y15                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
    SLICE_X96Y15         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/Q
                         net (fo=1, routed)           0.351     0.429    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[7]
    SLICE_X94Y21         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y21         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.429    
  -------------------------------------------------------------------
                         slack                                  2.596    

Slack (MET) :             2.602ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.423ns  (logic 0.079ns (18.676%)  route 0.344ns (81.324%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y12                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
    SLICE_X95Y12         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/Q
                         net (fo=1, routed)           0.344     0.423    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[0]
    SLICE_X93Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y12         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.423    
  -------------------------------------------------------------------
                         slack                                  2.602    

Slack (MET) :             2.621ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.404ns  (logic 0.078ns (19.307%)  route 0.326ns (80.693%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y8                                       0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
    SLICE_X96Y8          FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/Q
                         net (fo=1, routed)           0.326     0.404    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[6]
    SLICE_X93Y13         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y13         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.404    
  -------------------------------------------------------------------
                         slack                                  2.621    

Slack (MET) :             2.625ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.400ns  (logic 0.078ns (19.500%)  route 0.322ns (80.500%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y18                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
    SLICE_X96Y18         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/Q
                         net (fo=1, routed)           0.322     0.400    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[11]
    SLICE_X95Y22         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y22         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.400    
  -------------------------------------------------------------------
                         slack                                  2.625    

Slack (MET) :             2.640ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.385ns  (logic 0.079ns (20.519%)  route 0.306ns (79.481%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y24                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
    SLICE_X96Y24         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/Q
                         net (fo=1, routed)           0.306     0.385    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[13]
    SLICE_X95Y22         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y22         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.385    
  -------------------------------------------------------------------
                         slack                                  2.640    

Slack (MET) :             2.646ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.379ns  (logic 0.079ns (20.844%)  route 0.300ns (79.156%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y18                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
    SLICE_X96Y18         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/Q
                         net (fo=1, routed)           0.300     0.379    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[14]
    SLICE_X94Y13         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y13         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.379    
  -------------------------------------------------------------------
                         slack                                  2.646    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.755ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.755ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.270ns  (logic 0.079ns (6.222%)  route 1.191ns (93.778%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y63                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
    SLICE_X91Y63         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/Q
                         net (fo=29, routed)          1.191     1.270    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[1]
    SLICE_X95Y45         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y45         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.270    
  -------------------------------------------------------------------
                         slack                                  1.755    

Slack (MET) :             1.815ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.210ns  (logic 0.077ns (6.362%)  route 1.133ns (93.638%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y64                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
    SLICE_X93Y64         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=49, routed)          1.133     1.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[8]
    SLICE_X95Y45         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y45         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.210    
  -------------------------------------------------------------------
                         slack                                  1.815    

Slack (MET) :             1.826ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.199ns  (logic 0.078ns (6.507%)  route 1.121ns (93.493%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y65                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/C
    SLICE_X93Y65         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/Q
                         net (fo=13, routed)          1.121     1.199    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/D[0]
    SLICE_X93Y41         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y41         FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.199    
  -------------------------------------------------------------------
                         slack                                  1.826    

Slack (MET) :             1.887ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.138ns  (logic 0.079ns (6.940%)  route 1.059ns (93.060%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y63                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[15]/C
    SLICE_X91Y63         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[15]/Q
                         net (fo=33, routed)          1.059     1.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[15]
    SLICE_X94Y43         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y43         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[15].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.138    
  -------------------------------------------------------------------
                         slack                                  1.887    

Slack (MET) :             1.893ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.132ns  (logic 0.079ns (6.980%)  route 1.053ns (93.020%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y100                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
    SLICE_X90Y100        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/Q
                         net (fo=52, routed)          1.053     1.132    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X95Y43         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y43         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.132    
  -------------------------------------------------------------------
                         slack                                  1.893    

Slack (MET) :             2.044ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.981ns  (logic 0.076ns (7.744%)  route 0.905ns (92.256%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y100                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
    SLICE_X90Y100        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=52, routed)          0.905     0.981    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X93Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y44         FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.981    
  -------------------------------------------------------------------
                         slack                                  2.044    

Slack (MET) :             2.049ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.976ns  (logic 0.080ns (8.194%)  route 0.896ns (91.806%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y63                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[10]/C
    SLICE_X91Y63         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[10]/Q
                         net (fo=40, routed)          0.896     0.976    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[10]
    SLICE_X92Y50         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y50         FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[10].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.976    
  -------------------------------------------------------------------
                         slack                                  2.049    

Slack (MET) :             2.098ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.927ns  (logic 0.080ns (8.626%)  route 0.847ns (91.374%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y65                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/C
    SLICE_X93Y65         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/Q
                         net (fo=28, routed)          0.847     0.927    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X91Y42         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y42         FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.927    
  -------------------------------------------------------------------
                         slack                                  2.098    

Slack (MET) :             2.104ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[24].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.921ns  (logic 0.079ns (8.576%)  route 0.842ns (91.424%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y63                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[24]/C
    SLICE_X92Y63         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[24]/Q
                         net (fo=8, routed)           0.842     0.921    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[24]
    SLICE_X92Y45         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[24].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y45         FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[24].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.921    
  -------------------------------------------------------------------
                         slack                                  2.104    

Slack (MET) :             2.111ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.914ns  (logic 0.081ns (8.860%)  route 0.833ns (91.140%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y63                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/C
    SLICE_X91Y63         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/Q
                         net (fo=41, routed)          0.833     0.914    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[16]
    SLICE_X92Y61         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y61         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.914    
  -------------------------------------------------------------------
                         slack                                  2.111    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.739ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.531ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.739ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.616ns  (logic 0.079ns (4.889%)  route 1.537ns (95.111%))
  Logic Levels:           0  
  Clock Path Skew:        -0.457ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.808ns = ( 5.809 - 3.001 ) 
    Source Clock Delay      (SCD):    2.824ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.607ns (routing 0.764ns, distribution 0.843ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.607     2.824    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X84Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y48         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.903 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.537     4.440    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     5.494    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.600 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.675 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     5.797 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     5.809    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.367    
                         clock uncertainty           -0.170     5.197    
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.018     5.179    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.179    
                         arrival time                          -4.440    
  -------------------------------------------------------------------
                         slack                                  0.739    

Slack (MET) :             0.753ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.627ns  (logic 0.079ns (4.856%)  route 1.548ns (95.144%))
  Logic Levels:           0  
  Clock Path Skew:        -0.428ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.814ns = ( 5.815 - 3.001 ) 
    Source Clock Delay      (SCD):    2.801ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.584ns (routing 0.764ns, distribution 0.820ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.584     2.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_2
    SLICE_X88Y59         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y59         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.880 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.548     4.428    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y47 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     5.497    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.603 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.678 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     5.802 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.815    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y47 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.373    
                         clock uncertainty           -0.170     5.203    
    BITSLICE_RX_TX_X0Y47 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.022     5.181    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.181    
                         arrival time                          -4.428    
  -------------------------------------------------------------------
                         slack                                  0.753    

Slack (MET) :             0.754ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.588ns  (logic 0.079ns (4.975%)  route 1.509ns (95.025%))
  Logic Levels:           0  
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.828ns = ( 5.829 - 3.001 ) 
    Source Clock Delay      (SCD):    2.804ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.587ns (routing 0.764ns, distribution 0.823ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.587     2.804    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X88Y42         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y42         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.883 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.509     4.392    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.687 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.816 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.829    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.387    
                         clock uncertainty           -0.170     5.217    
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.071     5.146    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.146    
                         arrival time                          -4.392    
  -------------------------------------------------------------------
                         slack                                  0.754    

Slack (MET) :             0.756ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.420ns  (logic 0.079ns (5.564%)  route 1.341ns (94.436%))
  Logic Levels:           0  
  Clock Path Skew:        -0.540ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.686ns = ( 5.687 - 3.001 ) 
    Source Clock Delay      (SCD):    2.785ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.568ns (routing 0.764ns, distribution 0.804ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.695ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.568     2.785    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[13]
    SLICE_X85Y38         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y38         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.864 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/Q
                         net (fo=4, routed)           1.341     4.204    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.687 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.442     5.245    
                         clock uncertainty           -0.170     5.075    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.115     4.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.960    
                         arrival time                          -4.204    
  -------------------------------------------------------------------
                         slack                                  0.756    

Slack (MET) :             0.763ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.409ns  (logic 0.079ns (5.605%)  route 1.330ns (94.395%))
  Logic Levels:           0  
  Clock Path Skew:        -0.543ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.683ns = ( 5.684 - 3.001 ) 
    Source Clock Delay      (SCD):    2.785ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.568ns (routing 0.764ns, distribution 0.804ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.695ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.568     2.785    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[13]
    SLICE_X85Y38         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y38         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.864 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/Q
                         net (fo=4, routed)           1.330     4.194    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     5.492    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.609 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.684 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.442     5.242    
                         clock uncertainty           -0.170     5.072    
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.115     4.957    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.957    
                         arrival time                          -4.194    
  -------------------------------------------------------------------
                         slack                                  0.763    

Slack (MET) :             0.767ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.597ns  (logic 0.079ns (4.947%)  route 1.518ns (95.053%))
  Logic Levels:           0  
  Clock Path Skew:        -0.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.808ns = ( 5.809 - 3.001 ) 
    Source Clock Delay      (SCD):    2.808ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.591ns (routing 0.764ns, distribution 0.827ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.591     2.808    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X88Y47         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y47         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.518     4.405    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     5.494    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.600 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.675 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     5.797 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     5.809    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.367    
                         clock uncertainty           -0.170     5.197    
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.025     5.172    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.172    
                         arrival time                          -4.405    
  -------------------------------------------------------------------
                         slack                                  0.767    

Slack (MET) :             0.775ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.589ns  (logic 0.078ns (4.909%)  route 1.511ns (95.091%))
  Logic Levels:           0  
  Clock Path Skew:        -0.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.826ns = ( 5.827 - 3.001 ) 
    Source Clock Delay      (SCD):    2.814ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.597ns (routing 0.764ns, distribution 0.833ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.597     2.814    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X87Y46         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y46         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     2.892 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.511     4.403    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y3  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.687 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     5.815 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     5.827    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y3  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.385    
                         clock uncertainty           -0.170     5.215    
    BITSLICE_RX_TX_X0Y3  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.037     5.178    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.178    
                         arrival time                          -4.403    
  -------------------------------------------------------------------
                         slack                                  0.775    

Slack (MET) :             0.776ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.593ns  (logic 0.076ns (4.771%)  route 1.517ns (95.229%))
  Logic Levels:           0  
  Clock Path Skew:        -0.440ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.811ns = ( 5.812 - 3.001 ) 
    Source Clock Delay      (SCD):    2.810ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.593ns (routing 0.764ns, distribution 0.829ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.593     2.810    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X87Y43         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y43         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.886 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.517     4.403    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y8  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     5.494    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.600 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.675 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     5.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.812    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y8  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.370    
                         clock uncertainty           -0.170     5.200    
    BITSLICE_RX_TX_X0Y8  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.021     5.179    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.179    
                         arrival time                          -4.403    
  -------------------------------------------------------------------
                         slack                                  0.776    

Slack (MET) :             0.779ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.522ns  (logic 0.079ns (5.191%)  route 1.443ns (94.809%))
  Logic Levels:           0  
  Clock Path Skew:        -0.450ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.828ns = ( 5.829 - 3.001 ) 
    Source Clock Delay      (SCD):    2.837ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.620ns (routing 0.764ns, distribution 0.856ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.620     2.837    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X84Y3          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y3          FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           1.443     4.359    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.687 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.816 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.829    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.387    
                         clock uncertainty           -0.170     5.217    
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                     -0.079     5.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.138    
                         arrival time                          -4.359    
  -------------------------------------------------------------------
                         slack                                  0.779    

Slack (MET) :             0.779ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.570ns  (logic 0.079ns (5.032%)  route 1.491ns (94.968%))
  Logic Levels:           0  
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.832ns = ( 5.833 - 3.001 ) 
    Source Clock Delay      (SCD):    2.808ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.591ns (routing 0.764ns, distribution 0.827ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.591     2.808    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_0
    SLICE_X88Y47         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y47         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.491     4.378    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.262     6.022    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.392 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.687 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     5.818 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     5.833    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.442     5.391    
                         clock uncertainty           -0.170     5.221    
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.064     5.157    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.157    
                         arrival time                          -4.378    
  -------------------------------------------------------------------
                         slack                                  0.779    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.531ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.271ns  (logic 0.058ns (21.402%)  route 0.213ns (78.598%))
  Logic Levels:           0  
  Clock Path Skew:        -0.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.033ns
    Source Clock Delay      (SCD):    3.175ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.416ns (routing 0.695ns, distribution 0.721ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.764ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.416     3.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X82Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     3.233 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.213     3.446    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     2.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.442     2.475    
                         clock uncertainty            0.170     2.645    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     2.915    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.915    
                         arrival time                           3.446    
  -------------------------------------------------------------------
                         slack                                  0.531    

Slack (MET) :             0.574ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.058ns (18.650%)  route 0.253ns (81.350%))
  Logic Levels:           0  
  Clock Path Skew:        -0.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.033ns
    Source Clock Delay      (SCD):    3.175ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.415ns (routing 0.695ns, distribution 0.720ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.764ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     3.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X84Y3          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y3          FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.233 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.253     3.486    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     2.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.442     2.475    
                         clock uncertainty            0.170     2.645    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     2.912    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.912    
                         arrival time                           3.486    
  -------------------------------------------------------------------
                         slack                                  0.574    

Slack (MET) :             0.617ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.059ns (18.380%)  route 0.262ns (81.620%))
  Logic Levels:           0  
  Clock Path Skew:        -0.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.033ns
    Source Clock Delay      (SCD):    3.177ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.417ns (routing 0.695ns, distribution 0.722ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.764ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.417     3.177    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X84Y1          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y1          FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     3.236 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.262     3.498    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     2.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.442     2.475    
                         clock uncertainty            0.170     2.645    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.236     2.881    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.881    
                         arrival time                           3.498    
  -------------------------------------------------------------------
                         slack                                  0.617    

Slack (MET) :             0.622ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.360ns  (logic 0.059ns (16.389%)  route 0.301ns (83.611%))
  Logic Levels:           0  
  Clock Path Skew:        -0.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.033ns
    Source Clock Delay      (SCD):    3.175ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.415ns (routing 0.695ns, distribution 0.720ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.764ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     3.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X84Y1          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y1          FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.301     3.535    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     2.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.442     2.475    
                         clock uncertainty            0.170     2.645    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     2.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.913    
                         arrival time                           3.535    
  -------------------------------------------------------------------
                         slack                                  0.622    

Slack (MET) :             0.626ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.280ns  (logic 0.059ns (21.071%)  route 0.221ns (78.929%))
  Logic Levels:           0  
  Clock Path Skew:        -0.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.000ns
    Source Clock Delay      (SCD):    3.174ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.415ns (routing 0.695ns, distribution 0.720ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.764ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     3.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_upp/rsMask_reg[7][12]_0
    SLICE_X81Y5          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y5          FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.233 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_upp/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.221     3.454    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[3]
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.146     1.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     1.882 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     2.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.442     2.442    
                         clock uncertainty            0.170     2.612    
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.216     2.828    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.828    
                         arrival time                           3.454    
  -------------------------------------------------------------------
                         slack                                  0.626    

Slack (MET) :             0.630ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.363ns  (logic 0.059ns (16.253%)  route 0.304ns (83.747%))
  Logic Levels:           0  
  Clock Path Skew:        -0.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.027ns
    Source Clock Delay      (SCD):    3.176ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.417ns (routing 0.695ns, distribution 0.722ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.764ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.417     3.176    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y5          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y5          FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     3.235 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.304     3.539    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     1.715    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.908 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     2.027 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.442     2.469    
                         clock uncertainty            0.170     2.639    
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     2.909    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.909    
                         arrival time                           3.539    
  -------------------------------------------------------------------
                         slack                                  0.630    

Slack (MET) :             0.638ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.349ns  (logic 0.058ns (16.619%)  route 0.291ns (83.381%))
  Logic Levels:           0  
  Clock Path Skew:        -0.516ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.213ns
    Source Clock Delay      (SCD):    3.170ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.411ns (routing 0.695ns, distribution 0.716ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.411     3.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[13]_2
    SLICE_X83Y46         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y46         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     3.228 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[3]/Q
                         net (fo=1, routed)           0.291     3.519    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[3]
    BITSLICE_RX_TX_X0Y39 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     1.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.008 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     2.170 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     2.213    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y39 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.442     2.655    
                         clock uncertainty            0.170     2.825    
    BITSLICE_RX_TX_X0Y39 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.057     2.882    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.882    
                         arrival time                           3.519    
  -------------------------------------------------------------------
                         slack                                  0.638    

Slack (MET) :             0.659ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.379ns  (logic 0.058ns (15.303%)  route 0.321ns (84.697%))
  Logic Levels:           0  
  Clock Path Skew:        -0.516ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.213ns
    Source Clock Delay      (SCD):    3.170ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.411ns (routing 0.695ns, distribution 0.716ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.411     3.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[13]_2
    SLICE_X83Y46         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y46         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     3.228 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/Q
                         net (fo=1, routed)           0.321     3.549    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[5]
    BITSLICE_RX_TX_X0Y39 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     1.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.008 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     2.170 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     2.213    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y39 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.442     2.655    
                         clock uncertainty            0.170     2.825    
    BITSLICE_RX_TX_X0Y39 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.066     2.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.891    
                         arrival time                           3.549    
  -------------------------------------------------------------------
                         slack                                  0.659    

Slack (MET) :             0.661ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.060ns (15.707%)  route 0.322ns (84.293%))
  Logic Levels:           0  
  Clock Path Skew:        -0.525ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.208ns
    Source Clock Delay      (SCD):    3.175ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.415ns (routing 0.695ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.415     3.175    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[13]_2
    SLICE_X83Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y17         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     3.235 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/Q
                         net (fo=1, routed)           0.322     3.557    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y13 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     1.717    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.894 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     2.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     2.208    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y13 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.442     2.650    
                         clock uncertainty            0.170     2.820    
    BITSLICE_RX_TX_X0Y13 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.076     2.896    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.896    
                         arrival time                           3.557    
  -------------------------------------------------------------------
                         slack                                  0.661    

Slack (MET) :             0.665ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.061ns (15.969%)  route 0.321ns (84.031%))
  Logic Levels:           0  
  Clock Path Skew:        -0.505ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.211ns
    Source Clock Delay      (SCD):    3.157ns
    Clock Pessimism Removal (CPR):    -0.442ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.398ns (routing 0.695ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.398     3.157    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_2
    SLICE_X81Y23         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y23         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.218 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.321     3.539    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.415     2.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.574 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     1.717    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.894 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     2.190 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     2.211    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.442     2.653    
                         clock uncertainty            0.170     2.823    
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     2.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.875    
                         arrival time                           3.539    
  -------------------------------------------------------------------
                         slack                                  0.665    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.705ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.572ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.705ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.356ns  (logic 0.077ns (5.680%)  route 1.279ns (94.320%))
  Logic Levels:           0  
  Clock Path Skew:        -0.602ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.704ns = ( 5.705 - 3.001 ) 
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.651ns (routing 0.764ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.695ns, distribution 0.608ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.651     2.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X82Y64         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y64         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.945 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/Q
                         net (fo=7, routed)           1.279     4.224    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.091     5.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.705 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.438     5.267    
                         clock uncertainty           -0.170     5.097    
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.168     4.929    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.929    
                         arrival time                          -4.224    
  -------------------------------------------------------------------
                         slack                                  0.705    

Slack (MET) :             0.736ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.567ns  (logic 0.079ns (5.041%)  route 1.488ns (94.959%))
  Logic Levels:           0  
  Clock Path Skew:        -0.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.849ns = ( 5.850 - 3.001 ) 
    Source Clock Delay      (SCD):    2.863ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.646ns (routing 0.764ns, distribution 0.882ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.646     2.863    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y73         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y73         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.942 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][1]/Q
                         net (fo=1, routed)           1.488     4.430    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[1]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.099     5.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.638 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     5.837 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.850    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.412    
                         clock uncertainty           -0.170     5.242    
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.076     5.166    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.166    
                         arrival time                          -4.430    
  -------------------------------------------------------------------
                         slack                                  0.736    

Slack (MET) :             0.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.281ns  (logic 0.078ns (6.087%)  route 1.203ns (93.913%))
  Logic Levels:           0  
  Clock Path Skew:        -0.601ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.704ns = ( 5.705 - 3.001 ) 
    Source Clock Delay      (SCD):    2.867ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.650ns (routing 0.764ns, distribution 0.886ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.695ns, distribution 0.608ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.650     2.867    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X82Y64         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y64         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.945 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/Q
                         net (fo=7, routed)           1.203     4.148    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.091     5.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.705 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.438     5.267    
                         clock uncertainty           -0.170     5.097    
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     4.939    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.939    
                         arrival time                          -4.148    
  -------------------------------------------------------------------
                         slack                                  0.790    

Slack (MET) :             0.813ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][115]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.544ns  (logic 0.078ns (5.052%)  route 1.466ns (94.948%))
  Logic Levels:           0  
  Clock Path Skew:        -0.440ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.852ns = ( 5.853 - 3.001 ) 
    Source Clock Delay      (SCD):    2.855ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.638ns (routing 0.764ns, distribution 0.874ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.638     2.855    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X83Y90         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][115]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y90         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][115]/Q
                         net (fo=1, routed)           1.466     4.399    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y98 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.099     5.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.638 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     5.838 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     5.853    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y98 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.415    
                         clock uncertainty           -0.170     5.245    
    BITSLICE_RX_TX_X0Y98 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.033     5.212    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.212    
                         arrival time                          -4.399    
  -------------------------------------------------------------------
                         slack                                  0.813    

Slack (MET) :             0.813ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.526ns  (logic 0.077ns (5.046%)  route 1.449ns (94.954%))
  Logic Levels:           0  
  Clock Path Skew:        -0.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.868ns = ( 5.869 - 3.001 ) 
    Source Clock Delay      (SCD):    2.843ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.626ns (routing 0.764ns, distribution 0.862ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.626     2.843    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X82Y95         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y95         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.920 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][0]/Q
                         net (fo=1, routed)           1.449     4.369    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_BG[0]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.098     5.531    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.723 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     5.854 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     5.869    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.431    
                         clock uncertainty           -0.170     5.261    
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                     -0.079     5.182    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.182    
                         arrival time                          -4.369    
  -------------------------------------------------------------------
                         slack                                  0.813    

Slack (MET) :             0.818ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.588ns  (logic 0.079ns (4.975%)  route 1.509ns (95.025%))
  Logic Levels:           0  
  Clock Path Skew:        -0.413ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.868ns = ( 5.869 - 3.001 ) 
    Source Clock Delay      (SCD):    2.844ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.627ns (routing 0.764ns, distribution 0.863ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.627     2.844    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y99         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y99         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][3]/Q
                         net (fo=1, routed)           1.509     4.432    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_BG[3]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.098     5.531    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.723 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     5.854 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     5.869    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.431    
                         clock uncertainty           -0.170     5.261    
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.011     5.250    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.250    
                         arrival time                          -4.432    
  -------------------------------------------------------------------
                         slack                                  0.818    

Slack (MET) :             0.833ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.293ns  (logic 0.077ns (5.953%)  route 1.216ns (94.047%))
  Logic Levels:           0  
  Clock Path Skew:        -0.589ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.717ns = ( 5.718 - 3.001 ) 
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.651ns (routing 0.764ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.695ns, distribution 0.608ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.651     2.868    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X82Y64         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y64         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.945 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/Q
                         net (fo=7, routed)           1.216     4.161    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.093     5.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.643 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.718 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.438     5.280    
                         clock uncertainty           -0.170     5.110    
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.115     4.995    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.995    
                         arrival time                          -4.161    
  -------------------------------------------------------------------
                         slack                                  0.833    

Slack (MET) :             0.838ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.463ns  (logic 0.079ns (5.400%)  route 1.384ns (94.600%))
  Logic Levels:           0  
  Clock Path Skew:        -0.454ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.849ns = ( 5.850 - 3.001 ) 
    Source Clock Delay      (SCD):    2.865ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.648ns (routing 0.764ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.648     2.865    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X82Y68         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y68         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][0]/Q
                         net (fo=1, routed)           1.384     4.328    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[0]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.099     5.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.638 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     5.837 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.850    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.412    
                         clock uncertainty           -0.170     5.242    
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                     -0.076     5.166    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.166    
                         arrival time                          -4.328    
  -------------------------------------------------------------------
                         slack                                  0.838    

Slack (MET) :             0.841ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][133]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.532ns  (logic 0.078ns (5.091%)  route 1.454ns (94.909%))
  Logic Levels:           0  
  Clock Path Skew:        -0.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.864ns = ( 5.865 - 3.001 ) 
    Source Clock Delay      (SCD):    2.859ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.642ns (routing 0.764ns, distribution 0.878ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.642     2.859    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X87Y82         FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][133]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y82         FDSE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.937 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][133]/Q
                         net (fo=1, routed)           1.454     4.391    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y92 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.098     5.531    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.723 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.127     5.850 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     5.865    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y92 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.427    
                         clock uncertainty           -0.170     5.257    
    BITSLICE_RX_TX_X0Y92 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.025     5.232    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.232    
                         arrival time                          -4.391    
  -------------------------------------------------------------------
                         slack                                  0.841    

Slack (MET) :             0.845ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.520ns  (logic 0.079ns (5.197%)  route 1.441ns (94.803%))
  Logic Levels:           0  
  Clock Path Skew:        -0.444ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.849ns = ( 5.850 - 3.001 ) 
    Source Clock Delay      (SCD):    2.856ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.639ns (routing 0.764ns, distribution 0.875ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.639     2.856    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y75         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y75         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.935 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][2]/Q
                         net (fo=1, routed)           1.441     4.376    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[2]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.502 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.542 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.521 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.760 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.303     6.063    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.433 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.099     5.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.638 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     5.837 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.850    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.438     5.412    
                         clock uncertainty           -0.170     5.242    
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.021     5.221    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          5.221    
                         arrival time                          -4.376    
  -------------------------------------------------------------------
                         slack                                  0.845    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.572ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][67]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.058ns (18.650%)  route 0.253ns (81.350%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.253ns
    Source Clock Delay      (SCD):    3.195ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.436ns (routing 0.695ns, distribution 0.741ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.436     3.195    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X82Y96         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][67]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y96         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     3.253 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][67]/Q
                         net (fo=1, routed)           0.253     3.506    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     2.229 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     2.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.691    
                         clock uncertainty            0.170     2.861    
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.073     2.934    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.934    
                         arrival time                           3.506    
  -------------------------------------------------------------------
                         slack                                  0.572    

Slack (MET) :             0.596ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.318ns  (logic 0.059ns (18.553%)  route 0.259ns (81.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.242ns
    Source Clock Delay      (SCD):    3.194ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.434ns (routing 0.695ns, distribution 0.739ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.434     3.194    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y93         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y93         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     3.253 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/Q
                         net (fo=1, routed)           0.259     3.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     2.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     2.242    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.680    
                         clock uncertainty            0.170     2.850    
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.066     2.916    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.916    
                         arrival time                           3.512    
  -------------------------------------------------------------------
                         slack                                  0.596    

Slack (MET) :             0.603ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.309ns  (logic 0.060ns (19.417%)  route 0.249ns (80.583%))
  Logic Levels:           0  
  Clock Path Skew:        -0.507ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.253ns
    Source Clock Delay      (SCD):    3.198ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.438ns (routing 0.695ns, distribution 0.743ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.438     3.198    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y96         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y96         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.258 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/Q
                         net (fo=1, routed)           0.249     3.507    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[6]
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     2.229 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     2.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.691    
                         clock uncertainty            0.170     2.861    
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.043     2.904    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.904    
                         arrival time                           3.507    
  -------------------------------------------------------------------
                         slack                                  0.603    

Slack (MET) :             0.606ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][93]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.344ns  (logic 0.060ns (17.442%)  route 0.284ns (82.558%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.242ns
    Source Clock Delay      (SCD):    3.183ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.424ns (routing 0.695ns, distribution 0.729ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.424     3.183    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y92         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][93]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y92         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.243 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][93]/Q
                         net (fo=1, routed)           0.284     3.527    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     2.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     2.242    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.680    
                         clock uncertainty            0.170     2.850    
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.072     2.922    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.922    
                         arrival time                           3.527    
  -------------------------------------------------------------------
                         slack                                  0.606    

Slack (MET) :             0.608ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][87]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.061ns (19.614%)  route 0.250ns (80.386%))
  Logic Levels:           0  
  Clock Path Skew:        -0.509ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.245ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.432ns (routing 0.695ns, distribution 0.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.432     3.191    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y94         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][87]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y94         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.252 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][87]/Q
                         net (fo=1, routed)           0.250     3.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y81 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     2.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     2.245    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y81 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.683    
                         clock uncertainty            0.170     2.853    
    BITSLICE_RX_TX_X0Y81 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.041     2.894    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.894    
                         arrival time                           3.502    
  -------------------------------------------------------------------
                         slack                                  0.608    

Slack (MET) :             0.611ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.058ns (18.954%)  route 0.248ns (81.046%))
  Logic Levels:           0  
  Clock Path Skew:        -0.528ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.233ns
    Source Clock Delay      (SCD):    3.198ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.439ns (routing 0.695ns, distribution 0.744ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.439     3.198    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y83         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y83         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.256 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/Q
                         net (fo=1, routed)           0.248     3.504    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[2]
    BITSLICE_RX_TX_X0Y71 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.129     1.748    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     1.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.008 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     2.190 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     2.233    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y71 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.671    
                         clock uncertainty            0.170     2.841    
    BITSLICE_RX_TX_X0Y71 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.053     2.894    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.894    
                         arrival time                           3.504    
  -------------------------------------------------------------------
                         slack                                  0.611    

Slack (MET) :             0.619ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.363ns  (logic 0.060ns (16.529%)  route 0.303ns (83.471%))
  Logic Levels:           0  
  Clock Path Skew:        -0.511ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.241ns
    Source Clock Delay      (SCD):    3.189ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.430ns (routing 0.695ns, distribution 0.735ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.430     3.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y97         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y97         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/Q
                         net (fo=1, routed)           0.303     3.552    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[6]
    BITSLICE_RX_TX_X0Y84 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.137     1.756    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     1.907 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.016 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     2.198 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     2.241    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y84 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.679    
                         clock uncertainty            0.170     2.849    
    BITSLICE_RX_TX_X0Y84 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.085     2.934    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.934    
                         arrival time                           3.552    
  -------------------------------------------------------------------
                         slack                                  0.619    

Slack (MET) :             0.623ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.363ns  (logic 0.061ns (16.819%)  route 0.302ns (83.181%))
  Logic Levels:           0  
  Clock Path Skew:        -0.509ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.245ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.432ns (routing 0.695ns, distribution 0.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.432     3.191    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X82Y93         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y93         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     3.252 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/Q
                         net (fo=2, routed)           0.302     3.554    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq4[5]
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     2.223 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     2.245    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.683    
                         clock uncertainty            0.170     2.853    
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.078     2.931    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.931    
                         arrival time                           3.554    
  -------------------------------------------------------------------
                         slack                                  0.623    

Slack (MET) :             0.629ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.342ns  (logic 0.059ns (17.251%)  route 0.283ns (82.749%))
  Logic Levels:           0  
  Clock Path Skew:        -0.502ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.253ns
    Source Clock Delay      (SCD):    3.192ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.433ns (routing 0.695ns, distribution 0.738ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.433     3.192    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y95         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y95         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     3.251 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/Q
                         net (fo=1, routed)           0.283     3.534    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.132     1.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.037 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     2.229 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     2.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.691    
                         clock uncertainty            0.170     2.861    
    BITSLICE_RX_TX_X0Y83 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.044     2.905    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.905    
                         arrival time                           3.534    
  -------------------------------------------------------------------
                         slack                                  0.629    

Slack (MET) :             0.632ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.362ns  (logic 0.059ns (16.298%)  route 0.303ns (83.702%))
  Logic Levels:           0  
  Clock Path Skew:        -0.516ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.250ns
    Source Clock Delay      (SCD):    3.204ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.444ns (routing 0.695ns, distribution 0.749ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.444     3.204    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y101        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y101        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     3.263 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][0]/Q
                         net (fo=1, routed)           0.303     3.566    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27077, routed)       1.460     2.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y3             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.140     1.759    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.936 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     2.045 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     2.207 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     2.250    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.438     2.688    
                         clock uncertainty            0.170     2.858    
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.076     2.934    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.934    
                         arrival time                           3.566    
  -------------------------------------------------------------------
                         slack                                  0.632    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       49.536ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             49.536ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.489ns  (logic 0.078ns (15.951%)  route 0.411ns (84.049%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y3                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X97Y3          FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.411     0.489    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X98Y4          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X98Y4          FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.489    
  -------------------------------------------------------------------
                         slack                                 49.536    

Slack (MET) :             49.546ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.479ns  (logic 0.078ns (16.284%)  route 0.401ns (83.716%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y9                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X99Y9          FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.401     0.479    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X100Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X100Y11        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.479    
  -------------------------------------------------------------------
                         slack                                 49.546    

Slack (MET) :             49.643ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.382ns  (logic 0.076ns (19.895%)  route 0.306ns (80.105%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y9                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X99Y9          FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.306     0.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X100Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X100Y11        FDCE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.382    
  -------------------------------------------------------------------
                         slack                                 49.643    

Slack (MET) :             49.684ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.341ns  (logic 0.079ns (23.167%)  route 0.262ns (76.833%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X100Y9         FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.262     0.341    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X100Y9         FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.341    
  -------------------------------------------------------------------
                         slack                                 49.684    

Slack (MET) :             49.684ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.341ns  (logic 0.079ns (23.167%)  route 0.262ns (76.833%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y4                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X100Y4         FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.262     0.341    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X100Y4         FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.341    
  -------------------------------------------------------------------
                         slack                                 49.684    

Slack (MET) :             49.714ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.311ns  (logic 0.076ns (24.437%)  route 0.235ns (75.563%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y8                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X99Y8          FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.235     0.311    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X99Y8          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X99Y8          FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.311    
  -------------------------------------------------------------------
                         slack                                 49.714    

Slack (MET) :             49.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.281ns  (logic 0.080ns (28.470%)  route 0.201ns (71.530%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y3                                       0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X97Y3          FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.201     0.281    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X98Y4          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X98Y4          FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.281    
  -------------------------------------------------------------------
                         slack                                 49.744    

Slack (MET) :             49.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.281ns  (logic 0.079ns (28.114%)  route 0.202ns (71.886%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y4                                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X100Y4         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.202     0.281    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X100Y4         FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.281    
  -------------------------------------------------------------------
                         slack                                 49.744    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       11.567ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.567ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.458ns  (logic 0.081ns (17.686%)  route 0.377ns (82.314%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
    SLICE_X95Y17         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.377     0.458    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y11         FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.458    
  -------------------------------------------------------------------
                         slack                                 11.567    

Slack (MET) :             11.607ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.418ns  (logic 0.081ns (19.378%)  route 0.337ns (80.622%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
    SLICE_X95Y17         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.337     0.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y11         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.418    
  -------------------------------------------------------------------
                         slack                                 11.607    

Slack (MET) :             11.615ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.410ns  (logic 0.081ns (19.756%)  route 0.329ns (80.244%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
    SLICE_X95Y17         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.329     0.410    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y11         FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.410    
  -------------------------------------------------------------------
                         slack                                 11.615    

Slack (MET) :             11.643ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.382ns  (logic 0.079ns (20.665%)  route 0.303ns (79.335%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y2                                       0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
    SLICE_X93Y2          FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.303     0.382    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y2          FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.382    
  -------------------------------------------------------------------
                         slack                                 11.643    

Slack (MET) :             11.671ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.354ns  (logic 0.080ns (22.599%)  route 0.274ns (77.401%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
    SLICE_X95Y17         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.274     0.354    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X95Y9          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y9          FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.354    
  -------------------------------------------------------------------
                         slack                                 11.671    

Slack (MET) :             11.671ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.354ns  (logic 0.077ns (21.751%)  route 0.277ns (78.249%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y12                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
    SLICE_X96Y12         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.277     0.354    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y12         FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.354    
  -------------------------------------------------------------------
                         slack                                 11.671    

Slack (MET) :             11.720ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.305ns  (logic 0.081ns (26.557%)  route 0.224ns (73.443%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y12                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
    SLICE_X95Y12         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.224     0.305    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y12         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.305    
  -------------------------------------------------------------------
                         slack                                 11.720    

Slack (MET) :             11.721ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.304ns  (logic 0.080ns (26.316%)  route 0.224ns (73.684%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y12                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
    SLICE_X96Y12         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.224     0.304    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y12         FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.304    
  -------------------------------------------------------------------
                         slack                                 11.721    

Slack (MET) :             11.740ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.285ns  (logic 0.080ns (28.070%)  route 0.205ns (71.930%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y12                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
    SLICE_X95Y12         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.205     0.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y12         FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.285    
  -------------------------------------------------------------------
                         slack                                 11.740    

Slack (MET) :             11.763ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.262ns  (logic 0.080ns (30.534%)  route 0.182ns (69.466%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y10                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
    SLICE_X95Y10         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.182     0.262    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X96Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y10         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.262    
  -------------------------------------------------------------------
                         slack                                 11.763    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.446ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.151ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.446ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout0 rise@3.001ns)
  Data Path Delay:        1.157ns  (logic 0.190ns (16.422%)  route 0.967ns (83.578%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.234ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.152ns = ( 9.154 - 6.001 ) 
    Source Clock Delay      (SCD):    2.810ns = ( 5.810 - 3.001 ) 
    Clock Pessimism Removal (CPR):    -0.577ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.593ns (routing 0.764ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.381ns (routing 0.695ns, distribution 0.686ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     3.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     3.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     3.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     4.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     4.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.593     5.810    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X90Y43         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y43         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.366     6.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts
    SLICE_X82Y43         LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.112     6.366 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_hold_fix/O
                         net (fo=1, routed)           0.601     6.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_hold_fix_1_alias
    SLICE_X91Y49         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.503 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.543    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.543 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.522 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     7.749    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.773 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.381     9.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y49         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.577     8.577    
                         clock uncertainty           -0.188     8.388    
    SLICE_X91Y49         FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025     8.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                          8.413    
                         arrival time                          -6.967    
  -------------------------------------------------------------------
                         slack                                  1.446    

Slack (MET) :             4.278ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.747ns  (logic 0.081ns (10.843%)  route 0.666ns (89.157%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y39                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/C
    SLICE_X91Y39         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/Q
                         net (fo=1, routed)           0.666     0.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[1]
    SLICE_X91Y62         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X91Y62         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.747    
  -------------------------------------------------------------------
                         slack                                  4.278    

Slack (MET) :             4.284ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.741ns  (logic 0.076ns (10.256%)  route 0.665ns (89.744%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y42                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
    SLICE_X93Y42         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/Q
                         net (fo=1, routed)           0.665     0.741    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[14]
    SLICE_X92Y56         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y56         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.741    
  -------------------------------------------------------------------
                         slack                                  4.284    

Slack (MET) :             4.324ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.701ns  (logic 0.081ns (11.555%)  route 0.620ns (88.445%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y48                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[2]/C
    SLICE_X92Y48         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[2]/Q
                         net (fo=1, routed)           0.620     0.701    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[2]
    SLICE_X92Y62         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y62         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.701    
  -------------------------------------------------------------------
                         slack                                  4.324    

Slack (MET) :             4.397ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[28].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.628ns  (logic 0.079ns (12.580%)  route 0.549ns (87.420%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y48                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[28]/C
    SLICE_X92Y48         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[28]/Q
                         net (fo=1, routed)           0.549     0.628    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[28]
    SLICE_X91Y60         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[28].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X91Y60         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[28].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.628    
  -------------------------------------------------------------------
                         slack                                  4.397    

Slack (MET) :             4.422ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.603ns  (logic 0.081ns (13.433%)  route 0.522ns (86.567%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y37                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/C
    SLICE_X92Y37         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/Q
                         net (fo=1, routed)           0.522     0.603    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[25]
    SLICE_X92Y61         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y61         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.603    
  -------------------------------------------------------------------
                         slack                                  4.422    

Slack (MET) :             4.434ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[30].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.591ns  (logic 0.080ns (13.536%)  route 0.511ns (86.464%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y41                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[30]/C
    SLICE_X91Y41         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[30]/Q
                         net (fo=1, routed)           0.511     0.591    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[30]
    SLICE_X92Y64         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[30].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y64         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[30].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.591    
  -------------------------------------------------------------------
                         slack                                  4.434    

Slack (MET) :             4.439ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.586ns  (logic 0.080ns (13.652%)  route 0.506ns (86.348%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y40                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
    SLICE_X90Y40         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/Q
                         net (fo=1, routed)           0.506     0.586    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X92Y61         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y61         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.586    
  -------------------------------------------------------------------
                         slack                                  4.439    

Slack (MET) :             4.475ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.550ns  (logic 0.079ns (14.364%)  route 0.471ns (85.636%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y45                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
    SLICE_X92Y45         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/Q
                         net (fo=1, routed)           0.471     0.550    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[29]
    SLICE_X91Y58         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X91Y58         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.550    
  -------------------------------------------------------------------
                         slack                                  4.475    

Slack (MET) :             4.477ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.548ns  (logic 0.079ns (14.416%)  route 0.469ns (85.584%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y45                                      0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
    SLICE_X92Y45         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/Q
                         net (fo=1, routed)           0.469     0.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X92Y45         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y45         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.548    
  -------------------------------------------------------------------
                         slack                                  4.477    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.531ns  (logic 0.078ns (14.689%)  route 0.453ns (85.311%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.663ns
    Source Clock Delay      (SCD):    1.882ns
    Clock Pessimism Removal (CPR):    -0.365ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.877ns (routing 0.421ns, distribution 0.456ns)
  Clock Net Delay (Destination): 0.989ns (routing 0.473ns, distribution 0.516ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.877     1.882    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X90Y43         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y43         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.921 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.190     2.111    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts
    SLICE_X82Y43         LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.039     2.150 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_hold_fix/O
                         net (fo=1, routed)           0.263     2.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_hold_fix_1_alias
    SLICE_X91Y49         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.989     1.663    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y49         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.365     2.027    
                         clock uncertainty            0.188     2.216    
    SLICE_X91Y49         FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.046     2.262    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -2.262    
                         arrival time                           2.413    
  -------------------------------------------------------------------
                         slack                                  0.151    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  RFADC2_CLK
  To Clock:  RFADC2_CLK

Setup :            0  Failing Endpoints,  Worst Slack        2.101ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.261ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.101ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        1.685ns  (logic 0.076ns (4.511%)  route 1.609ns (95.489%))
  Logic Levels:           0  
  Clock Path Skew:        -0.182ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.495ns = ( 6.564 - 4.069 ) 
    Source Clock Delay      (SCD):    2.919ns
    Clock Pessimism Removal (CPR):    0.242ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.393ns (routing 1.062ns, distribution 1.331ns)
  Clock Net Delay (Destination): 2.109ns (routing 0.960ns, distribution 1.149ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.393     2.919    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X70Y203        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y203        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.995 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=150, routed)         1.609     4.604    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_alias
    SLICE_X74Y173        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.109     6.564    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y173        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.242     6.806    
                         clock uncertainty           -0.035     6.771    
    SLICE_X74Y173        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     6.705    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          6.705    
                         arrival time                          -4.604    
  -------------------------------------------------------------------
                         slack                                  2.101    

Slack (MET) :             3.194ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.654ns  (logic 0.078ns (11.918%)  route 0.576ns (88.082%))
  Logic Levels:           0  
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.457ns = ( 6.526 - 4.069 ) 
    Source Clock Delay      (SCD):    2.896ns
    Clock Pessimism Removal (CPR):    0.319ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.370ns (routing 1.062ns, distribution 1.308ns)
  Clock Net Delay (Destination): 2.071ns (routing 0.960ns, distribution 1.111ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.370     2.896    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X67Y111        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y111        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.974 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=67, routed)          0.576     3.550    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_10_alias
    SLICE_X62Y110        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.071     6.526    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X62Y110        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.319     6.845    
                         clock uncertainty           -0.035     6.810    
    SLICE_X62Y110        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     6.744    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          6.744    
                         arrival time                          -3.550    
  -------------------------------------------------------------------
                         slack                                  3.194    

Slack (MET) :             3.194ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.654ns  (logic 0.078ns (11.918%)  route 0.576ns (88.082%))
  Logic Levels:           0  
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.457ns = ( 6.526 - 4.069 ) 
    Source Clock Delay      (SCD):    2.896ns
    Clock Pessimism Removal (CPR):    0.319ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.370ns (routing 1.062ns, distribution 1.308ns)
  Clock Net Delay (Destination): 2.071ns (routing 0.960ns, distribution 1.111ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.370     2.896    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X67Y111        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y111        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.974 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=67, routed)          0.576     3.550    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_10_alias
    SLICE_X62Y110        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.071     6.526    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X62Y110        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.319     6.845    
                         clock uncertainty           -0.035     6.810    
    SLICE_X62Y110        FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066     6.744    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          6.744    
                         arrival time                          -3.550    
  -------------------------------------------------------------------
                         slack                                  3.194    

Slack (MET) :             3.357ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_21/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.069ns  (RFADC2_CLK rise@4.069ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.563ns  (logic 0.079ns (14.032%)  route 0.484ns (85.968%))
  Logic Levels:           0  
  Clock Path Skew:        -0.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.505ns = ( 6.574 - 4.069 ) 
    Source Clock Delay      (SCD):    2.919ns
    Clock Pessimism Removal (CPR):    0.366ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.393ns (routing 1.062ns, distribution 1.331ns)
  Clock Net Delay (Destination): 2.119ns (routing 0.960ns, distribution 1.159ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.393     2.919    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X73Y123        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_21/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y123        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.998 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_21/Q
                         net (fo=139, routed)         0.484     3.482    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_21_alias
    SLICE_X73Y130        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      4.069     4.069 r  
    RFADC_X0Y2           RFADC                        0.000     4.069 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     4.191 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.341    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.455 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.119     6.574    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X73Y130        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.366     6.940    
                         clock uncertainty           -0.035     6.905    
    SLICE_X73Y130        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066     6.839    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          6.839    
                         arrival time                          -3.482    
  -------------------------------------------------------------------
                         slack                                  3.357    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.261ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_21/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.261ns  (logic 0.039ns (14.951%)  route 0.222ns (85.049%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.819ns
    Source Clock Delay      (SCD):    1.566ns
    Clock Pessimism Removal (CPR):    0.233ns
  Clock Net Delay (Source):      1.304ns (routing 0.578ns, distribution 0.726ns)
  Clock Net Delay (Destination): 1.468ns (routing 0.648ns, distribution 0.820ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.304     1.566    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X73Y123        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_21/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y123        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.605 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_21/Q
                         net (fo=139, routed)         0.222     1.826    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_21_alias
    SLICE_X73Y130        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.468     1.819    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X73Y130        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.233     1.585    
    SLICE_X73Y130        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     1.565    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.565    
                         arrival time                           1.826    
  -------------------------------------------------------------------
                         slack                                  0.261    

Slack (MET) :             0.304ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.039ns (12.555%)  route 0.272ns (87.445%))
  Logic Levels:           0  
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.796ns
    Source Clock Delay      (SCD):    1.562ns
    Clock Pessimism Removal (CPR):    0.208ns
  Clock Net Delay (Source):      1.300ns (routing 0.578ns, distribution 0.722ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.648ns, distribution 0.797ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.300     1.562    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X67Y111        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y111        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.601 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=67, routed)          0.272     1.872    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_10_alias
    SLICE_X62Y110        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.445     1.796    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X62Y110        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.208     1.588    
    SLICE_X62Y110        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.568    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.568    
                         arrival time                           1.872    
  -------------------------------------------------------------------
                         slack                                  0.304    

Slack (MET) :             0.304ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.039ns (12.555%)  route 0.272ns (87.445%))
  Logic Levels:           0  
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.796ns
    Source Clock Delay      (SCD):    1.562ns
    Clock Pessimism Removal (CPR):    0.208ns
  Clock Net Delay (Source):      1.300ns (routing 0.578ns, distribution 0.722ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.648ns, distribution 0.797ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.300     1.562    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X67Y111        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y111        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.601 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=67, routed)          0.272     1.872    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_10_alias
    SLICE_X62Y110        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.445     1.796    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X62Y110        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.208     1.588    
    SLICE_X62Y110        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     1.568    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.568    
                         arrival time                           1.872    
  -------------------------------------------------------------------
                         slack                                  0.304    

Slack (MET) :             0.776ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.834ns  (logic 0.038ns (4.554%)  route 0.796ns (95.446%))
  Logic Levels:           0  
  Clock Path Skew:        0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.810ns
    Source Clock Delay      (SCD):    1.573ns
    Clock Pessimism Removal (CPR):    0.159ns
  Clock Net Delay (Source):      1.311ns (routing 0.578ns, distribution 0.733ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.648ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.311     1.573    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X70Y203        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y203        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.611 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=150, routed)         0.796     2.407    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_alias
    SLICE_X74Y173        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.459     1.810    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y173        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.159     1.651    
    SLICE_X74Y173        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.631    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.631    
                         arrival time                           2.407    
  -------------------------------------------------------------------
                         slack                                  0.776    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        2.279ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.013ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.279ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.380ns  (logic 0.107ns (4.496%)  route 2.273ns (95.504%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.333ns = ( 10.333 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.258ns (routing 1.400ns, distribution 0.858ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.445     7.617    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.258    10.333    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/C
                         clock pessimism             -0.309    10.024    
                         clock uncertainty           -0.062     9.962    
    SLICE_X70Y212        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.896    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]
  -------------------------------------------------------------------
                         required time                          9.896    
                         arrival time                          -7.617    
  -------------------------------------------------------------------
                         slack                                  2.279    

Slack (MET) :             2.279ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.380ns  (logic 0.107ns (4.496%)  route 2.273ns (95.504%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.333ns = ( 10.333 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.258ns (routing 1.400ns, distribution 0.858ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.445     7.617    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.258    10.333    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                         clock pessimism             -0.309    10.024    
                         clock uncertainty           -0.062     9.962    
    SLICE_X70Y212        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066     9.896    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                          9.896    
                         arrival time                          -7.617    
  -------------------------------------------------------------------
                         slack                                  2.279    

Slack (MET) :             2.280ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.107ns (4.501%)  route 2.270ns (95.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.215ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.331ns = ( 10.331 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.256ns (routing 1.400ns, distribution 0.856ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.442     7.614    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y210        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.256    10.331    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism             -0.309    10.022    
                         clock uncertainty           -0.062     9.960    
    SLICE_X70Y210        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     9.894    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                          9.894    
                         arrival time                          -7.614    
  -------------------------------------------------------------------
                         slack                                  2.280    

Slack (MET) :             2.280ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.107ns (4.501%)  route 2.270ns (95.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.215ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.331ns = ( 10.331 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.256ns (routing 1.400ns, distribution 0.856ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.442     7.614    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y210        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.256    10.331    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                         clock pessimism             -0.309    10.022    
                         clock uncertainty           -0.062     9.960    
    SLICE_X70Y210        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.894    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]
  -------------------------------------------------------------------
                         required time                          9.894    
                         arrival time                          -7.614    
  -------------------------------------------------------------------
                         slack                                  2.280    

Slack (MET) :             2.281ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.385ns  (logic 0.107ns (4.486%)  route 2.278ns (95.514%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.206ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.340ns = ( 10.340 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.265ns (routing 1.400ns, distribution 0.865ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.450     7.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X66Y233        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.265    10.340    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X66Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                         clock pessimism             -0.309    10.031    
                         clock uncertainty           -0.062     9.969    
    SLICE_X66Y233        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.903    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                          9.903    
                         arrival time                          -7.622    
  -------------------------------------------------------------------
                         slack                                  2.281    

Slack (MET) :             2.281ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.385ns  (logic 0.107ns (4.486%)  route 2.278ns (95.514%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.206ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.340ns = ( 10.340 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.265ns (routing 1.400ns, distribution 0.865ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.450     7.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X66Y233        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.265    10.340    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X66Y233        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism             -0.309    10.031    
                         clock uncertainty           -0.062     9.969    
    SLICE_X66Y233        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066     9.903    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                          9.903    
                         arrival time                          -7.622    
  -------------------------------------------------------------------
                         slack                                  2.281    

Slack (MET) :             2.281ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.107ns (4.501%)  route 2.270ns (95.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.332ns = ( 10.332 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.257ns (routing 1.400ns, distribution 0.857ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.442     7.614    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.257    10.332    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism             -0.309    10.023    
                         clock uncertainty           -0.062     9.961    
    SLICE_X70Y212        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066     9.895    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                          9.895    
                         arrival time                          -7.614    
  -------------------------------------------------------------------
                         slack                                  2.281    

Slack (MET) :             2.281ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.107ns (4.501%)  route 2.270ns (95.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.332ns = ( 10.332 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.257ns (routing 1.400ns, distribution 0.857ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.442     7.614    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.257    10.332    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
                         clock pessimism             -0.309    10.023    
                         clock uncertainty           -0.062     9.961    
    SLICE_X70Y212        FDCE (Recov_GFF_SLICEM_C_CLR)
                                                     -0.066     9.895    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]
  -------------------------------------------------------------------
                         required time                          9.895    
                         arrival time                          -7.614    
  -------------------------------------------------------------------
                         slack                                  2.281    

Slack (MET) :             2.281ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.107ns (4.501%)  route 2.270ns (95.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.332ns = ( 10.332 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.257ns (routing 1.400ns, distribution 0.857ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.442     7.614    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.257    10.332    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
                         clock pessimism             -0.309    10.023    
                         clock uncertainty           -0.062     9.961    
    SLICE_X70Y212        FDCE (Recov_FFF_SLICEM_C_CLR)
                                                     -0.066     9.895    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]
  -------------------------------------------------------------------
                         required time                          9.895    
                         arrival time                          -7.614    
  -------------------------------------------------------------------
                         slack                                  2.281    

Slack (MET) :             2.281ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.107ns (4.501%)  route 2.270ns (95.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.332ns = ( 10.332 - 5.000 ) 
    Source Clock Delay      (SCD):    5.237ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.616ns (routing 1.545ns, distribution 1.071ns)
  Clock Net Delay (Destination): 2.257ns (routing 1.400ns, distribution 0.857ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.616     5.237    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.316 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.828     6.144    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        1.442     7.614    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X70Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     7.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     8.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.257    10.332    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/C
                         clock pessimism             -0.309    10.023    
                         clock uncertainty           -0.062     9.961    
    SLICE_X70Y212        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066     9.895    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]
  -------------------------------------------------------------------
                         required time                          9.895    
                         arrival time                          -7.614    
  -------------------------------------------------------------------
                         slack                                  2.281    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.013ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.130ns  (logic 0.056ns (4.958%)  route 1.074ns (95.042%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.686ns (routing 0.950ns, distribution 0.736ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.647     4.320    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y277        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.686     3.108    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y277        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                         clock pessimism              0.219     3.327    
    SLICE_X84Y277        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.307    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.307    
                         arrival time                           4.320    
  -------------------------------------------------------------------
                         slack                                  1.013    

Slack (MET) :             1.013ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.130ns  (logic 0.056ns (4.958%)  route 1.074ns (95.042%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.686ns (routing 0.950ns, distribution 0.736ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.647     4.320    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y277        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.686     3.108    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y277        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                         clock pessimism              0.219     3.327    
    SLICE_X84Y277        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.307    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.307    
                         arrival time                           4.320    
  -------------------------------------------------------------------
                         slack                                  1.013    

Slack (MET) :             1.014ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.126ns  (logic 0.056ns (4.975%)  route 1.070ns (95.025%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.103ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.681ns (routing 0.950ns, distribution 0.731ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.643     4.316    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y271        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.681     3.103    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y271        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism              0.219     3.322    
    SLICE_X84Y271        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.302    
                         arrival time                           4.316    
  -------------------------------------------------------------------
                         slack                                  1.014    

Slack (MET) :             1.014ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.126ns  (logic 0.056ns (4.975%)  route 1.070ns (95.025%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.103ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.681ns (routing 0.950ns, distribution 0.731ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.643     4.316    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y271        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.681     3.103    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y271        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/C
                         clock pessimism              0.219     3.322    
    SLICE_X84Y271        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.302    
                         arrival time                           4.316    
  -------------------------------------------------------------------
                         slack                                  1.014    

Slack (MET) :             1.014ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.128ns  (logic 0.056ns (4.967%)  route 1.072ns (95.033%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.133ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.683ns (routing 0.950ns, distribution 0.733ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.645     4.318    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y269        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.683     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y269        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                         clock pessimism              0.219     3.324    
    SLICE_X84Y269        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.304    
                         arrival time                           4.318    
  -------------------------------------------------------------------
                         slack                                  1.014    

Slack (MET) :             1.014ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.128ns  (logic 0.056ns (4.967%)  route 1.072ns (95.033%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.133ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.683ns (routing 0.950ns, distribution 0.733ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.645     4.318    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y269        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.683     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y269        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                         clock pessimism              0.219     3.324    
    SLICE_X84Y269        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.304    
                         arrival time                           4.318    
  -------------------------------------------------------------------
                         slack                                  1.014    

Slack (MET) :             1.014ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.128ns  (logic 0.056ns (4.967%)  route 1.072ns (95.033%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.133ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.683ns (routing 0.950ns, distribution 0.733ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.645     4.318    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y269        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.683     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y269        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                         clock pessimism              0.219     3.324    
    SLICE_X84Y269        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     3.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.304    
                         arrival time                           4.318    
  -------------------------------------------------------------------
                         slack                                  1.014    

Slack (MET) :             1.017ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.130ns  (logic 0.056ns (4.958%)  route 1.074ns (95.042%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.132ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.104ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.682ns (routing 0.950ns, distribution 0.732ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.647     4.320    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y277        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.682     3.104    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y277        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism              0.219     3.323    
    SLICE_X84Y277        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     3.303    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.303    
                         arrival time                           4.320    
  -------------------------------------------------------------------
                         slack                                  1.017    

Slack (MET) :             1.017ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.130ns  (logic 0.056ns (4.958%)  route 1.074ns (95.042%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.132ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.104ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.682ns (routing 0.950ns, distribution 0.732ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.647     4.320    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y277        FDPE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.682     3.104    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y277        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
                         clock pessimism              0.219     3.323    
    SLICE_X84Y277        FDPE (Remov_CFF2_SLICEL_C_PRE)
                                                     -0.020     3.303    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.303    
                         arrival time                           4.320    
  -------------------------------------------------------------------
                         slack                                  1.017    

Slack (MET) :             1.017ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.130ns  (logic 0.056ns (4.958%)  route 1.074ns (95.042%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.132ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.104ns
    Source Clock Delay      (SCD):    3.191ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.442ns (routing 0.846ns, distribution 0.596ns)
  Clock Net Delay (Destination): 1.682ns (routing 0.950ns, distribution 0.732ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.442     3.191    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.230 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.427     3.657    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y128        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.674 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=2481, routed)        0.647     4.320    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X84Y277        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.682     3.104    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X84Y277        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                         clock pessimism              0.219     3.323    
    SLICE_X84Y277        FDCE (Remov_BFF2_SLICEL_C_CLR)
                                                     -0.020     3.303    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.303    
                         arrival time                           4.320    
  -------------------------------------------------------------------
                         slack                                  1.017    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        7.252ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.149ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.252ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][12]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.175ns  (logic 0.107ns (4.920%)  route 2.068ns (95.080%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.377ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.115ns = ( 12.115 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.691ns, distribution 1.242ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.422     4.784    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y260        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.933    12.115    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y260        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][12]/C
                         clock pessimism              0.117    12.232    
                         clock uncertainty           -0.130    12.102    
    SLICE_X56Y260        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.036    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][12]
  -------------------------------------------------------------------
                         required time                         12.036    
                         arrival time                          -4.784    
  -------------------------------------------------------------------
                         slack                                  7.252    

Slack (MET) :             7.256ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.154ns  (logic 0.107ns (4.967%)  route 2.047ns (95.033%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.394ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.098ns = ( 12.098 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.916ns (routing 0.691ns, distribution 1.225ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.401     4.763    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y275        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.916    12.098    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y275        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]/C
                         clock pessimism              0.117    12.215    
                         clock uncertainty           -0.130    12.085    
    SLICE_X56Y275        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.019    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]
  -------------------------------------------------------------------
                         required time                         12.019    
                         arrival time                          -4.763    
  -------------------------------------------------------------------
                         slack                                  7.256    

Slack (MET) :             7.258ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][11]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.162ns  (logic 0.107ns (4.949%)  route 2.055ns (95.051%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.108ns = ( 12.108 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.926ns (routing 0.691ns, distribution 1.235ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.409     4.771    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.926    12.108    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][11]/C
                         clock pessimism              0.117    12.225    
                         clock uncertainty           -0.130    12.095    
    SLICE_X56Y262        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.029    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][11]
  -------------------------------------------------------------------
                         required time                         12.029    
                         arrival time                          -4.771    
  -------------------------------------------------------------------
                         slack                                  7.258    

Slack (MET) :             7.260ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.146ns  (logic 0.107ns (4.986%)  route 2.039ns (95.014%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.094ns = ( 12.094 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.912ns (routing 0.691ns, distribution 1.221ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.393     4.755    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X55Y276        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.912    12.094    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X55Y276        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/C
                         clock pessimism              0.117    12.211    
                         clock uncertainty           -0.130    12.081    
    SLICE_X55Y276        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    12.015    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]
  -------------------------------------------------------------------
                         required time                         12.015    
                         arrival time                          -4.755    
  -------------------------------------------------------------------
                         slack                                  7.260    

Slack (MET) :             7.260ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][5]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.159ns  (logic 0.107ns (4.956%)  route 2.052ns (95.044%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.385ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.107ns = ( 12.107 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.925ns (routing 0.691ns, distribution 1.234ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.406     4.768    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.925    12.107    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][5]/C
                         clock pessimism              0.117    12.224    
                         clock uncertainty           -0.130    12.094    
    SLICE_X56Y262        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    12.028    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][5]
  -------------------------------------------------------------------
                         required time                         12.028    
                         arrival time                          -4.768    
  -------------------------------------------------------------------
                         slack                                  7.260    

Slack (MET) :             7.262ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][16]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.138ns  (logic 0.107ns (5.005%)  route 2.031ns (94.995%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.088ns = ( 12.088 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.906ns (routing 0.691ns, distribution 1.215ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.385     4.747    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y271        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][16]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.906    12.088    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y271        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][16]/C
                         clock pessimism              0.117    12.205    
                         clock uncertainty           -0.130    12.075    
    SLICE_X56Y271        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.009    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][16]
  -------------------------------------------------------------------
                         required time                         12.009    
                         arrival time                          -4.747    
  -------------------------------------------------------------------
                         slack                                  7.262    

Slack (MET) :             7.262ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.138ns  (logic 0.107ns (5.005%)  route 2.031ns (94.995%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.088ns = ( 12.088 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.906ns (routing 0.691ns, distribution 1.215ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.385     4.747    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y271        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.906    12.088    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y271        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]/C
                         clock pessimism              0.117    12.205    
                         clock uncertainty           -0.130    12.075    
    SLICE_X56Y271        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    12.009    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]
  -------------------------------------------------------------------
                         required time                         12.009    
                         arrival time                          -4.747    
  -------------------------------------------------------------------
                         slack                                  7.262    

Slack (MET) :             7.263ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.145ns  (logic 0.107ns (4.988%)  route 2.038ns (95.012%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.396ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.096ns = ( 12.096 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.691ns, distribution 1.223ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.392     4.754    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X55Y276        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.914    12.096    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X55Y276        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]/C
                         clock pessimism              0.117    12.213    
                         clock uncertainty           -0.130    12.083    
    SLICE_X55Y276        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    12.017    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]
  -------------------------------------------------------------------
                         required time                         12.017    
                         arrival time                          -4.754    
  -------------------------------------------------------------------
                         slack                                  7.263    

Slack (MET) :             7.263ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][20]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.143ns  (logic 0.107ns (4.993%)  route 2.036ns (95.007%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.094ns = ( 12.094 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.912ns (routing 0.691ns, distribution 1.221ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.390     4.752    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y277        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][20]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.912    12.094    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y277        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][20]/C
                         clock pessimism              0.117    12.211    
                         clock uncertainty           -0.130    12.081    
    SLICE_X56Y277        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    12.015    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][20]
  -------------------------------------------------------------------
                         required time                         12.015    
                         arrival time                          -4.752    
  -------------------------------------------------------------------
                         slack                                  7.263    

Slack (MET) :             7.263ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][11]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.164ns  (logic 0.107ns (4.945%)  route 2.057ns (95.055%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.377ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.115ns = ( 12.115 - 10.000 ) 
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.691ns, distribution 1.242ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y119        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y119        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.646     3.334    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.362 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=15371, routed)       1.411     4.773    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X56Y240        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.933    12.115    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X56Y240        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][11]/C
                         clock pessimism              0.117    12.232    
                         clock uncertainty           -0.130    12.102    
    SLICE_X56Y240        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.036    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][11]
  -------------------------------------------------------------------
                         required time                         12.036    
                         arrival time                          -4.773    
  -------------------------------------------------------------------
                         slack                                  7.263    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.149ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.054ns (34.456%)  route 0.103ns (65.544%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.525ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.378ns (routing 0.463ns, distribution 0.915ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.077     1.492    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.378     1.525    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
                         clock pessimism             -0.161     1.364    
    SLICE_X35Y152        FDPE (Remov_DFF2_SLICEM_C_PRE)
                                                     -0.020     1.344    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
  -------------------------------------------------------------------
                         required time                         -1.344    
                         arrival time                           1.492    
  -------------------------------------------------------------------
                         slack                                  0.149    

Slack (MET) :             0.149ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.054ns (34.456%)  route 0.103ns (65.544%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.525ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.378ns (routing 0.463ns, distribution 0.915ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.077     1.492    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDCE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.378     1.525    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDCE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
                         clock pessimism             -0.161     1.364    
    SLICE_X35Y152        FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     1.344    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.344    
                         arrival time                           1.492    
  -------------------------------------------------------------------
                         slack                                  0.149    

Slack (MET) :             0.149ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.054ns (34.456%)  route 0.103ns (65.544%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.525ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.378ns (routing 0.463ns, distribution 0.915ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.077     1.492    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDCE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.378     1.525    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDCE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
                         clock pessimism             -0.161     1.364    
    SLICE_X35Y152        FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     1.344    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.344    
                         arrival time                           1.492    
  -------------------------------------------------------------------
                         slack                                  0.149    

Slack (MET) :             0.149ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.054ns (34.456%)  route 0.103ns (65.544%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.525ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.378ns (routing 0.463ns, distribution 0.915ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.077     1.492    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDCE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.378     1.525    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDCE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
                         clock pessimism             -0.161     1.364    
    SLICE_X35Y152        FDCE (Remov_BFF2_SLICEM_C_CLR)
                                                     -0.020     1.344    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
  -------------------------------------------------------------------
                         required time                         -1.344    
                         arrival time                           1.492    
  -------------------------------------------------------------------
                         slack                                  0.149    

Slack (MET) :             0.150ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.156ns  (logic 0.054ns (34.677%)  route 0.102ns (65.323%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.523ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.376ns (routing 0.463ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.076     1.491    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.376     1.523    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
                         clock pessimism             -0.161     1.362    
    SLICE_X35Y152        FDPE (Remov_EFF_SLICEM_C_PRE)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.491    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.150ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.156ns  (logic 0.054ns (34.677%)  route 0.102ns (65.323%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.523ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.376ns (routing 0.463ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.076     1.491    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.376     1.523    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C
                         clock pessimism             -0.161     1.362    
    SLICE_X35Y152        FDPE (Remov_EFF2_SLICEM_C_PRE)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.491    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.150ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.156ns  (logic 0.054ns (34.677%)  route 0.102ns (65.323%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.523ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.376ns (routing 0.463ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.076     1.491    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.376     1.523    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
                         clock pessimism             -0.161     1.362    
    SLICE_X35Y152        FDPE (Remov_FFF_SLICEM_C_PRE)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.491    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.150ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.156ns  (logic 0.054ns (34.677%)  route 0.102ns (65.323%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.523ns
    Source Clock Delay      (SCD):    1.336ns
    Clock Pessimism Removal (CPR):    0.161ns
  Clock Net Delay (Source):      1.216ns (routing 0.414ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.376ns (routing 0.463ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.216     1.336    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X36Y151        FDRE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.375 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.026     1.400    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X36Y152        LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.415 f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.076     1.491    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X35Y152        FDPE                                         f  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.376     1.523    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X35Y152        FDPE                                         r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C
                         clock pessimism             -0.161     1.362    
    SLICE_X35Y152        FDPE (Remov_FFF2_SLICEM_C_PRE)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.491    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.055ns (24.287%)  route 0.171ns (75.713%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    1.287ns
    Clock Pessimism Removal (CPR):    0.130ns
  Clock Net Delay (Source):      1.167ns (routing 0.414ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.463ns, distribution 0.886ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.167     1.287    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X58Y152        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y152        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.328 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.071     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X58Y152        LUT3 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.014     1.413 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.100     1.513    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X62Y152        FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.349     1.496    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X62Y152        FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]/C
                         clock pessimism             -0.130     1.367    
    SLICE_X62Y152        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.347    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.347    
                         arrival time                           1.513    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.055ns (24.287%)  route 0.171ns (75.713%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    1.287ns
    Clock Pessimism Removal (CPR):    0.130ns
  Clock Net Delay (Source):      1.167ns (routing 0.414ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.463ns, distribution 0.886ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.167     1.287    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X58Y152        FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y152        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.328 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.071     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X58Y152        LUT3 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.014     1.413 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.100     1.513    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X62Y152        FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.349     1.496    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X62Y152        FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                         clock pessimism             -0.130     1.367    
    SLICE_X62Y152        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     1.347    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.347    
                         arrival time                           1.513    
  -------------------------------------------------------------------
                         slack                                  0.166    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       48.651ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.094ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             48.651ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.192ns  (logic 0.367ns (30.788%)  route 0.825ns (69.212%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.947ns = ( 54.947 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.419ns (routing 1.653ns, distribution 0.766ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.476    11.293    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X99Y18         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.419    54.947    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              5.099    60.045    
                         clock uncertainty           -0.035    60.010    
    SLICE_X99Y18         FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    59.944    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         59.944    
                         arrival time                         -11.293    
  -------------------------------------------------------------------
                         slack                                 48.651    

Slack (MET) :             48.689ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.143ns  (logic 0.367ns (32.108%)  route 0.776ns (67.892%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.067ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.936ns = ( 54.936 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.408ns (routing 1.653ns, distribution 0.755ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.427    11.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X99Y19         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.408    54.936    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              5.099    60.034    
                         clock uncertainty           -0.035    59.999    
    SLICE_X99Y19         FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    59.933    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         59.933    
                         arrival time                         -11.244    
  -------------------------------------------------------------------
                         slack                                 48.689    

Slack (MET) :             48.689ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.143ns  (logic 0.367ns (32.108%)  route 0.776ns (67.892%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.067ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.936ns = ( 54.936 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.408ns (routing 1.653ns, distribution 0.755ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.427    11.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X99Y19         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.408    54.936    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              5.099    60.034    
                         clock uncertainty           -0.035    59.999    
    SLICE_X99Y19         FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    59.933    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         59.933    
                         arrival time                         -11.244    
  -------------------------------------------------------------------
                         slack                                 48.689    

Slack (MET) :             48.689ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.143ns  (logic 0.367ns (32.108%)  route 0.776ns (67.892%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.067ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.936ns = ( 54.936 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.408ns (routing 1.653ns, distribution 0.755ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.427    11.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X99Y19         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.408    54.936    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              5.099    60.034    
                         clock uncertainty           -0.035    59.999    
    SLICE_X99Y19         FDCE (Recov_FFF_SLICEM_C_CLR)
                                                     -0.066    59.933    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         59.933    
                         arrival time                         -11.244    
  -------------------------------------------------------------------
                         slack                                 48.689    

Slack (MET) :             48.689ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.143ns  (logic 0.367ns (32.108%)  route 0.776ns (67.892%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.067ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.936ns = ( 54.936 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.099ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.408ns (routing 1.653ns, distribution 0.755ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.427    11.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X99Y19         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.408    54.936    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X99Y19         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              5.099    60.034    
                         clock uncertainty           -0.035    59.999    
    SLICE_X99Y19         FDCE (Recov_FFF2_SLICEM_C_CLR)
                                                     -0.066    59.933    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         59.933    
                         arrival time                         -11.244    
  -------------------------------------------------------------------
                         slack                                 48.689    

Slack (MET) :             48.792ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.088ns  (logic 0.367ns (33.747%)  route 0.721ns (66.253%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.935ns = ( 54.935 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.147ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.407ns (routing 1.653ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.371    11.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X97Y18         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407    54.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              5.147    60.082    
                         clock uncertainty           -0.035    60.046    
    SLICE_X97Y18         FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    59.980    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                         59.980    
                         arrival time                         -11.189    
  -------------------------------------------------------------------
                         slack                                 48.792    

Slack (MET) :             48.792ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.088ns  (logic 0.367ns (33.747%)  route 0.721ns (66.253%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.935ns = ( 54.935 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.147ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.407ns (routing 1.653ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.371    11.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X97Y18         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407    54.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              5.147    60.082    
                         clock uncertainty           -0.035    60.046    
    SLICE_X97Y18         FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    59.980    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         59.980    
                         arrival time                         -11.189    
  -------------------------------------------------------------------
                         slack                                 48.792    

Slack (MET) :             48.792ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.088ns  (logic 0.367ns (33.747%)  route 0.721ns (66.253%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.935ns = ( 54.935 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.147ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.407ns (routing 1.653ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.371    11.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X97Y18         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407    54.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
                         clock pessimism              5.147    60.082    
                         clock uncertainty           -0.035    60.046    
    SLICE_X97Y18         FDCE (Recov_FFF_SLICEM_C_CLR)
                                                     -0.066    59.980    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
  -------------------------------------------------------------------
                         required time                         59.980    
                         arrival time                         -11.189    
  -------------------------------------------------------------------
                         slack                                 48.792    

Slack (MET) :             48.792ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.088ns  (logic 0.367ns (33.747%)  route 0.721ns (66.253%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.935ns = ( 54.935 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.147ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.407ns (routing 1.653ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.371    11.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X97Y18         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407    54.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              5.147    60.082    
                         clock uncertainty           -0.035    60.046    
    SLICE_X97Y18         FDCE (Recov_FFF2_SLICEM_C_CLR)
                                                     -0.066    59.980    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         59.980    
                         arrival time                         -11.189    
  -------------------------------------------------------------------
                         slack                                 48.792    

Slack (MET) :             48.792ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        1.088ns  (logic 0.367ns (33.747%)  route 0.721ns (66.253%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.935ns = ( 54.935 - 50.000 ) 
    Source Clock Delay      (SCD):    10.101ns
    Clock Pessimism Removal (CPR):    5.147ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.688ns (routing 1.824ns, distribution 0.864ns)
  Clock Net Delay (Destination): 2.407ns (routing 1.653ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.688    10.101    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y28         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y28         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081    10.182 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[3]/Q
                         net (fo=1, routed)           0.198    10.380    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[3]
    SLICE_X98Y28         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150    10.530 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.151    10.681    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X98Y25         LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.136    10.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.371    11.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X97Y18         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039    52.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.407    54.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X97Y18         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              5.147    60.082    
                         clock uncertainty           -0.035    60.046    
    SLICE_X97Y18         FDCE (Recov_GFF_SLICEM_C_CLR)
                                                     -0.066    59.980    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         59.980    
                         arrival time                         -11.189    
  -------------------------------------------------------------------
                         slack                                 48.792    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.040ns (30.075%)  route 0.093ns (69.925%))
  Logic Levels:           0  
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.147ns
    Source Clock Delay      (SCD):    3.585ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.492ns (routing 0.999ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.702ns (routing 1.125ns, distribution 0.577ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.492     3.585    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y3         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y3         FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.625 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.093     3.718    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X100Y3         FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.702     8.147    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X100Y3         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism             -4.503     3.644    
    SLICE_X100Y3         FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                     -0.020     3.624    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -3.624    
                         arrival time                           3.718    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.145ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.700ns (routing 1.125ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X98Y7          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.700     8.145    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
                         clock pessimism             -4.503     3.642    
    SLICE_X98Y7          FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -3.622    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.145ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.700ns (routing 1.125ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X98Y7          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.700     8.145    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C
                         clock pessimism             -4.503     3.642    
    SLICE_X98Y7          FDPE (Remov_EFF2_SLICEL_C_PRE)
                                                     -0.020     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -3.622    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.145ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.700ns (routing 1.125ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X98Y7          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.700     8.145    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
                         clock pessimism             -4.503     3.642    
    SLICE_X98Y7          FDPE (Remov_FFF_SLICEL_C_PRE)
                                                     -0.020     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -3.622    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.145ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.700ns (routing 1.125ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X98Y7          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.700     8.145    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C
                         clock pessimism             -4.503     3.642    
    SLICE_X98Y7          FDPE (Remov_FFF2_SLICEL_C_PRE)
                                                     -0.020     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -3.622    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.145ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.700ns (routing 1.125ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg_0[0]
    SLICE_X98Y7          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.700     8.145    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
                         clock pessimism             -4.503     3.642    
    SLICE_X98Y7          FDPE (Remov_GFF_SLICEL_C_PRE)
                                                     -0.020     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -3.622    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.145ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.700ns (routing 1.125ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg_0[0]
    SLICE_X98Y7          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.700     8.145    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X98Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                         clock pessimism             -4.503     3.642    
    SLICE_X98Y7          FDPE (Remov_GFF2_SLICEL_C_PRE)
                                                     -0.020     3.622    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg
  -------------------------------------------------------------------
                         required time                         -3.622    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.113ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.141ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.696ns (routing 1.125ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X98Y7          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.696     8.141    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
                         clock pessimism             -4.503     3.638    
    SLICE_X98Y7          FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     3.618    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.618    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.113    

Slack (MET) :             0.113ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.472%)  route 0.106ns (73.528%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.141ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.503ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.696ns (routing 1.125ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y7          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y7          FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.626 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.106     3.731    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X98Y7          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.696     8.141    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X98Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
                         clock pessimism             -4.503     3.638    
    SLICE_X98Y7          FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     3.618    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.618    
                         arrival time                           3.731    
  -------------------------------------------------------------------
                         slack                                  0.113    

Slack (MET) :             0.117ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.040ns (35.714%)  route 0.072ns (64.286%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.140ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    4.537ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.695ns (routing 1.125ns, distribution 0.570ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X100Y6         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y6         FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     3.628 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/Q
                         net (fo=1, routed)           0.072     3.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2
    SLICE_X99Y6          FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.695     8.140    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X99Y6          FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C
                         clock pessimism             -4.537     3.603    
    SLICE_X99Y6          FDPE (Remov_HFF2_SLICEM_C_PRE)
                                                     -0.020     3.583    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -3.583    
                         arrival time                           3.700    
  -------------------------------------------------------------------
                         slack                                  0.117    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.833ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.126ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.833ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.940ns  (logic 0.079ns (8.401%)  route 0.861ns (91.599%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.228 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.702ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.861     3.823    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X103Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473    15.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.722    
    SLICE_X103Y11        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    14.656    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[19]
  -------------------------------------------------------------------
                         required time                         14.656    
                         arrival time                          -3.823    
  -------------------------------------------------------------------
                         slack                                 10.833    

Slack (MET) :             10.833ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.940ns  (logic 0.079ns (8.401%)  route 0.861ns (91.599%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.228 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.702ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.861     3.823    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X103Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473    15.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.722    
    SLICE_X103Y11        FDCE (Recov_CFF2_SLICEM_C_CLR)
                                                     -0.066    14.656    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]
  -------------------------------------------------------------------
                         required time                         14.656    
                         arrival time                          -3.823    
  -------------------------------------------------------------------
                         slack                                 10.833    

Slack (MET) :             10.835ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[0]/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.937ns  (logic 0.079ns (8.428%)  route 0.858ns (91.572%))
  Logic Levels:           0  
  Clock Path Skew:        -0.089ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.224ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.858     3.820    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X103Y11        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y11        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[0]/C
                         clock pessimism             -0.430    14.796    
                         clock uncertainty           -0.076    14.721    
    SLICE_X103Y11        FDPE (Recov_EFF_SLICEM_C_PRE)
                                                     -0.066    14.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[0]
  -------------------------------------------------------------------
                         required time                         14.655    
                         arrival time                          -3.820    
  -------------------------------------------------------------------
                         slack                                 10.835    

Slack (MET) :             10.894ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.879ns  (logic 0.079ns (8.991%)  route 0.800ns (91.009%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.800     3.761    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.721    
    SLICE_X102Y11        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    14.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]
  -------------------------------------------------------------------
                         required time                         14.655    
                         arrival time                          -3.761    
  -------------------------------------------------------------------
                         slack                                 10.894    

Slack (MET) :             10.894ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.879ns  (logic 0.079ns (8.991%)  route 0.800ns (91.009%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.800     3.761    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.721    
    SLICE_X102Y11        FDCE (Recov_BFF_SLICEL_C_CLR)
                                                     -0.066    14.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]
  -------------------------------------------------------------------
                         required time                         14.655    
                         arrival time                          -3.761    
  -------------------------------------------------------------------
                         slack                                 10.894    

Slack (MET) :             10.894ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.879ns  (logic 0.079ns (8.991%)  route 0.800ns (91.009%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.800     3.761    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X101Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.721    
    SLICE_X101Y11        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    14.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]
  -------------------------------------------------------------------
                         required time                         14.655    
                         arrival time                          -3.761    
  -------------------------------------------------------------------
                         slack                                 10.894    

Slack (MET) :             10.894ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.879ns  (logic 0.079ns (8.991%)  route 0.800ns (91.009%))
  Logic Levels:           0  
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns = ( 15.227 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.702ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.800     3.761    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X101Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.472    15.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/C
                         clock pessimism             -0.430    14.797    
                         clock uncertainty           -0.076    14.721    
    SLICE_X101Y11        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    14.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]
  -------------------------------------------------------------------
                         required time                         14.655    
                         arrival time                          -3.761    
  -------------------------------------------------------------------
                         slack                                 10.894    

Slack (MET) :             10.897ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.878ns  (logic 0.079ns (9.001%)  route 0.799ns (90.999%))
  Logic Levels:           0  
  Clock Path Skew:        -0.086ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.227ns = ( 15.229 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.474ns (routing 0.702ns, distribution 0.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.799     3.760    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.474    15.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/C
                         clock pessimism             -0.430    14.799    
                         clock uncertainty           -0.076    14.723    
    SLICE_X102Y11        FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                     -0.066    14.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]
  -------------------------------------------------------------------
                         required time                         14.657    
                         arrival time                          -3.760    
  -------------------------------------------------------------------
                         slack                                 10.897    

Slack (MET) :             10.897ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.878ns  (logic 0.079ns (9.001%)  route 0.799ns (90.999%))
  Logic Levels:           0  
  Clock Path Skew:        -0.086ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.227ns = ( 15.229 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.474ns (routing 0.702ns, distribution 0.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.799     3.760    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X102Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.474    15.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X102Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]/C
                         clock pessimism             -0.430    14.799    
                         clock uncertainty           -0.076    14.723    
    SLICE_X102Y11        FDCE (Recov_GFF2_SLICEL_C_CLR)
                                                     -0.066    14.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[11]
  -------------------------------------------------------------------
                         required time                         14.657    
                         arrival time                          -3.760    
  -------------------------------------------------------------------
                         slack                                 10.897    

Slack (MET) :             10.897ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.878ns  (logic 0.079ns (9.001%)  route 0.799ns (90.999%))
  Logic Levels:           0  
  Clock Path Skew:        -0.086ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.227ns = ( 15.229 - 12.002 ) 
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    -0.430ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.675ns (routing 0.773ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.474ns (routing 0.702ns, distribution 0.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.675     2.882    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.961 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.799     3.760    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X101Y11        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.504 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.544    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.544 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.523 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208    13.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.755 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.474    15.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X101Y11        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/C
                         clock pessimism             -0.430    14.799    
                         clock uncertainty           -0.076    14.723    
    SLICE_X101Y11        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    14.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]
  -------------------------------------------------------------------
                         required time                         14.657    
                         arrival time                          -3.760    
  -------------------------------------------------------------------
                         slack                                 10.897    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.126ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.159ns  (logic 0.039ns (24.508%)  route 0.120ns (75.492%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.049ns (routing 0.477ns, distribution 0.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y5         FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.957 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.120     2.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X100Y5         FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.049     1.706    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X100Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
                         clock pessimism              0.266     1.972    
    SLICE_X100Y5         FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     1.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.952    
                         arrival time                           2.078    
  -------------------------------------------------------------------
                         slack                                  0.126    

Slack (MET) :             0.126ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.159ns  (logic 0.039ns (24.508%)  route 0.120ns (75.492%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.049ns (routing 0.477ns, distribution 0.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y5         FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.957 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.120     2.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X100Y5         FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.049     1.706    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X100Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                         clock pessimism              0.266     1.972    
    SLICE_X100Y5         FDPE (Remov_EFF2_SLICEL_C_PRE)
                                                     -0.020     1.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg
  -------------------------------------------------------------------
                         required time                         -1.952    
                         arrival time                           2.078    
  -------------------------------------------------------------------
                         slack                                  0.126    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.163ns  (logic 0.040ns (24.530%)  route 0.123ns (75.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.050ns (routing 0.477ns, distribution 0.573ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y4         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y4         FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.123     2.082    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X100Y4         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.050     1.707    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/C
                         clock pessimism              0.266     1.973    
    SLICE_X100Y4         FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     1.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.953    
                         arrival time                           2.082    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.163ns  (logic 0.040ns (24.530%)  route 0.123ns (75.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.050ns (routing 0.477ns, distribution 0.573ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y4         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y4         FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.123     2.082    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X100Y4         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.050     1.707    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C
                         clock pessimism              0.266     1.973    
    SLICE_X100Y4         FDCE (Remov_GFF2_SLICEL_C_CLR)
                                                     -0.020     1.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.953    
                         arrival time                           2.082    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.163ns  (logic 0.040ns (24.530%)  route 0.123ns (75.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.050ns (routing 0.477ns, distribution 0.573ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y4         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y4         FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.123     2.082    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X100Y4         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.050     1.707    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/C
                         clock pessimism              0.266     1.973    
    SLICE_X100Y4         FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     1.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.953    
                         arrival time                           2.082    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.163ns  (logic 0.040ns (24.530%)  route 0.123ns (75.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.050ns (routing 0.477ns, distribution 0.573ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y4         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y4         FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.123     2.082    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X100Y4         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.050     1.707    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]/C
                         clock pessimism              0.266     1.973    
    SLICE_X100Y4         FDCE (Remov_FFF2_SLICEL_C_CLR)
                                                     -0.020     1.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.953    
                         arrival time                           2.082    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.163ns  (logic 0.040ns (24.530%)  route 0.123ns (75.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.050ns (routing 0.477ns, distribution 0.573ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y4         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y4         FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.123     2.082    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X100Y4         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.050     1.707    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X100Y4         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                         clock pessimism              0.266     1.973    
    SLICE_X100Y4         FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.953    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.953    
                         arrival time                           2.082    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.165ns  (logic 0.039ns (23.617%)  route 0.126ns (76.383%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.052ns (routing 0.477ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y5         FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.957 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.126     2.084    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X99Y5          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.052     1.709    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X99Y5          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C
                         clock pessimism              0.266     1.975    
    SLICE_X99Y5          FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     1.955    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.955    
                         arrival time                           2.084    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.165ns  (logic 0.039ns (23.617%)  route 0.126ns (76.383%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.052ns (routing 0.477ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y5         FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.957 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.126     2.084    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X99Y5          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.052     1.709    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X99Y5          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C
                         clock pessimism              0.266     1.975    
    SLICE_X99Y5          FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     1.955    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.955    
                         arrival time                           2.084    
  -------------------------------------------------------------------
                         slack                                  0.129    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.165ns  (logic 0.039ns (23.617%)  route 0.126ns (76.383%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.266ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.052ns (routing 0.477ns, distribution 0.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.918    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X102Y5         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y5         FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.957 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.126     2.084    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X99Y5          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.052     1.709    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X99Y5          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C
                         clock pessimism              0.266     1.975    
    SLICE_X99Y5          FDCE (Remov_FFF_SLICEM_C_CLR)
                                                     -0.020     1.955    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.955    
                         arrival time                           2.084    
  -------------------------------------------------------------------
                         slack                                  0.129    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.616ns  (logic 2.440ns (52.853%)  route 2.176ns (47.147%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.509ns (routing 1.864ns, distribution 1.645ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.509     4.220    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X82Y249        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y249        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.298 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           2.176     6.475    PMOD0_1_LS_OBUF
    G16                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.362     8.836 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.836    PMOD0_1_LS
    G16                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.613ns  (logic 2.463ns (53.395%)  route 2.150ns (46.605%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.388ns (routing 1.864ns, distribution 1.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.388     4.099    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X79Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y231        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.177 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           2.150     6.327    PMOD0_7_LS_OBUF
    J14                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.385     8.712 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.712    PMOD0_7_LS
    J14                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.454ns  (logic 2.444ns (54.869%)  route 2.010ns (45.131%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.359ns (routing 1.864ns, distribution 1.495ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.359     4.070    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X80Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y230        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.149 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.010     6.159    PMOD0_3_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.365     8.524 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.524    PMOD0_3_LS
    H15                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.379ns  (logic 2.443ns (55.782%)  route 1.936ns (44.218%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.427ns (routing 1.864ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.427     4.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X77Y246        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y246        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.219 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           1.936     6.155    PMOD0_0_LS_OBUF
    G15                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.362     8.517 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.517    PMOD0_0_LS
    G15                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.286ns  (logic 2.439ns (56.904%)  route 1.847ns (43.096%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.388ns (routing 1.864ns, distribution 1.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.388     4.099    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X79Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y231        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.177 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           1.847     6.024    PMOD0_4_LS_OBUF
    G13                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.361     8.385 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.385    PMOD0_4_LS
    G13                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.275ns  (logic 2.463ns (57.612%)  route 1.812ns (42.388%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.395ns (routing 1.864ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.395     4.106    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.185 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           1.812     5.997    PMOD0_6_LS_OBUF
    J13                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.384     8.381 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.381    PMOD0_6_LS
    J13                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.175ns  (logic 2.443ns (58.511%)  route 1.732ns (41.489%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.387ns (routing 1.864ns, distribution 1.523ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.387     4.098    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y262        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.177 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           1.732     5.909    PMOD0_2_LS_OBUF
    H14                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.364     8.273 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     8.273    PMOD0_2_LS
    H14                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.738ns  (logic 2.441ns (65.318%)  route 1.296ns (34.682%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.509ns (routing 1.864ns, distribution 1.645ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.509     4.220    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X82Y249        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y249        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.298 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           1.296     5.595    PMOD0_5_LS_OBUF
    H13                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.363     7.958 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.958    PMOD0_5_LS
    H13                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.828ns  (logic 1.144ns (62.573%)  route 0.684ns (37.427%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.912ns (routing 1.007ns, distribution 0.905ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.912     2.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X82Y249        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y249        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     2.317 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           0.684     3.001    PMOD0_5_LS_OBUF
    H13                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.106     4.106 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.106    PMOD0_5_LS
    H13                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.028ns  (logic 1.145ns (56.464%)  route 0.883ns (43.536%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.846ns (routing 1.007ns, distribution 0.839ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.846     2.213    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y262        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.252 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           0.883     3.135    PMOD0_2_LS_OBUF
    H14                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.106     4.241 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.241    PMOD0_2_LS
    H14                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.042ns  (logic 1.143ns (55.963%)  route 0.899ns (44.037%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.839ns (routing 1.007ns, distribution 0.832ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.839     2.206    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X79Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y231        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.245 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           0.899     3.144    PMOD0_4_LS_OBUF
    G13                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.104     4.247 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.247    PMOD0_4_LS
    G13                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.078ns  (logic 1.165ns (56.074%)  route 0.913ns (43.927%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.848ns (routing 1.007ns, distribution 0.841ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.848     2.215    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y251        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y251        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.254 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           0.913     3.166    PMOD0_6_LS_OBUF
    J13                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.126     4.292 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.292    PMOD0_6_LS
    J13                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.080ns  (logic 1.145ns (55.061%)  route 0.935ns (44.939%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.860ns (routing 1.007ns, distribution 0.853ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.860     2.227    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X77Y246        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y246        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.268 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           0.935     3.202    PMOD0_0_LS_OBUF
    G15                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.104     4.306 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.306    PMOD0_0_LS
    G15                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.165ns  (logic 1.146ns (52.944%)  route 1.019ns (47.056%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.829ns (routing 1.007ns, distribution 0.822ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.829     2.196    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X80Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y230        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.235 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.019     3.253    PMOD0_3_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.107     4.360 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.360    PMOD0_3_LS
    H15                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.267ns  (logic 1.165ns (51.405%)  route 1.102ns (48.594%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.839ns (routing 1.007ns, distribution 0.832ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.839     2.206    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X79Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y231        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     2.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           1.102     3.345    PMOD0_7_LS_OBUF
    J14                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.127     4.473 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.473    PMOD0_7_LS
    J14                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.241ns  (logic 1.143ns (51.004%)  route 1.098ns (48.996%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.912ns (routing 1.007ns, distribution 0.905ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.912     2.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X82Y249        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y249        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.318 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           1.098     3.416    PMOD0_1_LS_OBUF
    G16                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.104     4.520 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     4.520    PMOD0_1_LS
    G16                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFADC2_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.293ns  (logic 0.097ns (4.231%)  route 2.196ns (95.769%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.146ns (routing 0.960ns, distribution 1.186ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           1.770     1.770    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X79Y115        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.097     1.867 r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.426     2.293    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X77Y115        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.146     2.532    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X77Y115        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.062ns  (logic 0.037ns (3.485%)  route 1.025ns (96.515%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.495ns (routing 0.648ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           0.859     0.859    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X79Y115        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.037     0.896 r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.166     1.062    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X77Y115        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.495     1.846    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X77Y115        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  RFADC2_CLK

Max Delay           184 Endpoints
Min Delay           184 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.061ns  (logic 0.246ns (6.058%)  route 3.815ns (93.942%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.368ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.732ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.346ns (routing 0.960ns, distribution 1.386ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.434     7.647    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X115Y143       LUT1 (Prop_E5LUT_SLICEM_I0_O)
                                                      0.139     7.786 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.375     8.161    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.346     2.732    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.849ns  (logic 0.079ns (9.302%)  route 0.770ns (90.698%))
  Logic Levels:           0  
  Clock Path Skew:        -1.619ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.495ns
    Source Clock Delay      (SCD):    4.114ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.403ns (routing 1.864ns, distribution 1.539ns)
  Clock Net Delay (Destination): 2.109ns (routing 0.960ns, distribution 1.149ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.403     4.114    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y240        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y240        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.193 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.770     4.964    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X74Y173        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.109     2.495    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y173        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.582ns  (logic 0.080ns (13.735%)  route 0.502ns (86.265%))
  Logic Levels:           0  
  Clock Path Skew:        -1.591ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.732ns
    Source Clock Delay      (SCD):    4.323ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.612ns (routing 1.864ns, distribution 1.748ns)
  Clock Net Delay (Destination): 2.346ns (routing 0.960ns, distribution 1.386ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.612     4.323    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X114Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y144       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.403 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=149, routed)         0.502     4.905    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.346     2.732    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.780ns  (logic 0.078ns (9.996%)  route 0.702ns (90.004%))
  Logic Levels:           0  
  Clock Path Skew:        -1.640ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.483ns
    Source Clock Delay      (SCD):    4.123ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.412ns (routing 1.864ns, distribution 1.548ns)
  Clock Net Delay (Destination): 2.097ns (routing 0.960ns, distribution 1.137ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.412     4.123    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y243        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y243        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.201 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.702     4.904    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X63Y220        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.097     2.483    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X63Y220        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.761ns  (logic 0.079ns (10.377%)  route 0.682ns (89.623%))
  Logic Levels:           0  
  Clock Path Skew:        -1.641ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    4.068ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.357ns (routing 1.864ns, distribution 1.493ns)
  Clock Net Delay (Destination): 2.041ns (routing 0.960ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.357     4.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X76Y227        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y227        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.147 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.682     4.829    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X58Y226        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.041     2.427    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X58Y226        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.690ns  (logic 0.147ns (8.696%)  route 1.543ns (91.304%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.525ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.547ns
    Source Clock Delay      (SCD):    4.072ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.361ns (routing 1.864ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.960ns, distribution 1.201ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.361     4.072    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X78Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y231        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.151 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/Q
                         net (fo=296, routed)         1.309     5.460    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X79Y226        LUT2 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.068     5.528 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][1]_i_1/O
                         net (fo=1, routed)           0.234     5.762    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[1]
    SLICE_X79Y226        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.161     2.547    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X79Y226        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[227]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.606ns  (logic 0.307ns (19.116%)  route 1.299ns (80.884%))
  Logic Levels:           0  
  Clock Path Skew:        -1.558ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.537ns
    Source Clock Delay      (SCD):    4.095ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.384ns (routing 1.864ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.151ns (routing 0.960ns, distribution 1.191ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.384     4.095    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/WCLK
    SLICE_X78Y226        RAMD32                                       r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y226        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     4.402 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAMB_D1/O
                         net (fo=1, routed)           1.299     5.701    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[227]
    SLICE_X78Y218        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[227]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.151     2.537    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X78Y218        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[227]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.514ns  (logic 0.176ns (11.622%)  route 1.338ns (88.378%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.521ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.551ns
    Source Clock Delay      (SCD):    4.072ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.361ns (routing 1.864ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.165ns (routing 0.960ns, distribution 1.205ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.361     4.072    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X78Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y231        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.151 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/Q
                         net (fo=296, routed)         1.308     5.459    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X79Y224        LUT2 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.097     5.556 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.030     5.586    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X79Y224        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.165     2.551    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X79Y224        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[196]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.950ns  (logic 0.289ns (30.421%)  route 0.661ns (69.579%))
  Logic Levels:           0  
  Clock Path Skew:        -1.583ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.514ns
    Source Clock Delay      (SCD):    4.097ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.386ns (routing 1.864ns, distribution 1.522ns)
  Clock Net Delay (Destination): 2.128ns (routing 0.960ns, distribution 1.168ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.386     4.097    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/WCLK
    SLICE_X76Y234        RAMD32                                       r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y234        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     4.386 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMA/O
                         net (fo=1, routed)           0.661     5.047    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[196]
    SLICE_X73Y217        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[196]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.128     2.514    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X73Y217        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[196]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[44]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.944ns  (logic 0.292ns (30.932%)  route 0.652ns (69.068%))
  Logic Levels:           0  
  Clock Path Skew:        -1.572ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.518ns
    Source Clock Delay      (SCD):    4.090ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.379ns (routing 1.864ns, distribution 1.515ns)
  Clock Net Delay (Destination): 2.132ns (routing 0.960ns, distribution 1.172ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.379     4.090    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/WCLK
    SLICE_X75Y227        RAMD32                                       r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y227        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     4.382 r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/RAMB/O
                         net (fo=1, routed)           0.652     5.034    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[44]
    SLICE_X70Y220        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[44]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.132     2.518    d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X70Y220        FDRE                                         r  d_1_i/axis_cdcsync_v1_2/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[44]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.117ns  (logic 0.039ns (33.333%)  route 0.078ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.373ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.963ns
    Source Clock Delay      (SCD):    2.336ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.007ns, distribution 0.962ns)
  Clock Net Delay (Destination): 1.612ns (routing 0.648ns, distribution 0.964ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.969     2.336    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y144       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.375 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.078     2.453    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X117Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.612     1.963    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X117Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.038ns (31.405%)  route 0.083ns (68.595%))
  Logic Levels:           0  
  Clock Path Skew:        -0.373ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.962ns
    Source Clock Delay      (SCD):    2.335ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 1.007ns, distribution 0.961ns)
  Clock Net Delay (Destination): 1.611ns (routing 0.648ns, distribution 0.963ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.968     2.335    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X115Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y144       FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.373 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.083     2.456    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X115Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.611     1.962    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X115Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.954ns
    Source Clock Delay      (SCD):    2.336ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.007ns, distribution 0.962ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.648ns, distribution 0.955ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.969     2.336    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y144       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.375 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.090     2.465    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.603     1.954    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.351%)  route 0.109ns (73.649%))
  Logic Levels:           0  
  Clock Path Skew:        -0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.954ns
    Source Clock Delay      (SCD):    2.336ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.007ns, distribution 0.962ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.648ns, distribution 0.955ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.969     2.336    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y144       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.375 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.109     2.484    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.603     1.954    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.200ns  (logic 0.040ns (20.000%)  route 0.160ns (80.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.373ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.963ns
    Source Clock Delay      (SCD):    2.336ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.969ns (routing 1.007ns, distribution 0.962ns)
  Clock Net Delay (Destination): 1.612ns (routing 0.648ns, distribution 0.964ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.969     2.336    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X117Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y144       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.376 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.160     2.536    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X117Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.612     1.963    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X117Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.363ns  (logic 0.039ns (10.741%)  route 0.324ns (89.259%))
  Logic Levels:           0  
  Clock Path Skew:        -0.426ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.769ns
    Source Clock Delay      (SCD):    2.195ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.828ns (routing 1.007ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.418ns (routing 0.648ns, distribution 0.770ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.828     2.195    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X76Y227        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y227        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.234 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.324     2.558    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X58Y226        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.418     1.769    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X58Y226        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.370ns  (logic 0.038ns (10.268%)  route 0.332ns (89.732%))
  Logic Levels:           0  
  Clock Path Skew:        -0.419ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.805ns
    Source Clock Delay      (SCD):    2.224ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.857ns (routing 1.007ns, distribution 0.850ns)
  Clock Net Delay (Destination): 1.454ns (routing 0.648ns, distribution 0.806ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.857     2.224    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y243        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y243        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.262 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.332     2.594    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X63Y220        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.454     1.805    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X63Y220        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.265ns  (logic 0.039ns (14.724%)  route 0.226ns (85.276%))
  Logic Levels:           0  
  Clock Path Skew:        -0.366ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.973ns
    Source Clock Delay      (SCD):    2.339ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.972ns (routing 1.007ns, distribution 0.965ns)
  Clock Net Delay (Destination): 1.622ns (routing 0.648ns, distribution 0.974ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.972     2.339    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X114Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y144       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.378 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=149, routed)         0.226     2.603    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.622     1.973    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.412ns  (logic 0.039ns (9.464%)  route 0.373ns (90.536%))
  Logic Levels:           0  
  Clock Path Skew:        -0.409ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.810ns
    Source Clock Delay      (SCD):    2.219ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 1.007ns, distribution 0.845ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.648ns, distribution 0.811ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.852     2.219    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y240        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y240        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.258 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.373     2.631    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X74Y173        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.459     1.810    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X74Y173        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.110ns  (logic 0.105ns (4.976%)  route 2.005ns (95.024%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.244ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.973ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 1.622ns (routing 0.648ns, distribution 0.974ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.793     4.114    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X115Y143       LUT1 (Prop_E5LUT_SLICEM_I0_O)
                                                      0.049     4.163 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.164     4.327    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.622     1.973    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X115Y143       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFADC2_CLK

Max Delay           228 Endpoints
Min Delay           228 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.626ns  (logic 0.078ns (12.460%)  route 0.548ns (87.540%))
  Logic Levels:           0  
  Clock Path Skew:        -0.046ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.707ns
    Source Clock Delay      (SCD):    2.753ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.527ns (routing 0.764ns, distribution 1.763ns)
  Clock Net Delay (Destination): 2.321ns (routing 0.960ns, distribution 1.361ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.527     2.753    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X110Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y157       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/Q
                         net (fo=1, routed)           0.548     3.379    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/src_in
    SLICE_X116Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.321     2.707    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/dest_clk
    SLICE_X116Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.370ns  (logic 0.076ns (20.530%)  route 0.294ns (79.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    2.372ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.146ns (routing 0.764ns, distribution 1.382ns)
  Clock Net Delay (Destination): 2.037ns (routing 0.960ns, distribution 1.077ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.146     2.372    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X46Y221        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.448 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.294     2.742    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X48Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.037     2.423    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X48Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.303ns  (logic 0.076ns (25.080%)  route 0.227ns (74.920%))
  Logic Levels:           0  
  Clock Path Skew:        0.021ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.387ns
    Source Clock Delay      (SCD):    2.366ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.140ns (routing 0.764ns, distribution 1.376ns)
  Clock Net Delay (Destination): 2.001ns (routing 0.960ns, distribution 1.041ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.140     2.366    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X54Y168        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.442 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.227     2.669    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X56Y167        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.001     2.387    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X56Y167        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.108ns  (logic 0.228ns (20.574%)  route 0.880ns (79.426%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.371ns
    Source Clock Delay      (SCD):    2.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.105ns (routing 0.764ns, distribution 1.341ns)
  Clock Net Delay (Destination): 1.985ns (routing 0.960ns, distribution 1.025ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.105     2.331    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y193        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y193        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.410 r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[6]/Q
                         net (fo=2, routed)           0.832     3.242    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[6]
    SLICE_X52Y149        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     3.391 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[6]_i_1__0/O
                         net (fo=1, routed)           0.048     3.439    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[6]
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.985     2.371    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.106ns  (logic 0.204ns (18.444%)  route 0.902ns (81.556%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.047ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.378ns
    Source Clock Delay      (SCD):    2.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.105ns (routing 0.764ns, distribution 1.341ns)
  Clock Net Delay (Destination): 1.992ns (routing 0.960ns, distribution 1.032ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.105     2.331    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y193        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y193        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.412 r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[5]/Q
                         net (fo=2, routed)           0.851     3.263    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[5]
    SLICE_X52Y148        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.386 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[5]_i_1__0/O
                         net (fo=1, routed)           0.051     3.437    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[5]
    SLICE_X52Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.992     2.378    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X52Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.055ns  (logic 0.180ns (17.064%)  route 0.875ns (82.936%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.451ns
    Source Clock Delay      (SCD):    2.327ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.101ns (routing 0.764ns, distribution 1.337ns)
  Clock Net Delay (Destination): 2.065ns (routing 0.960ns, distribution 1.105ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.101     2.327    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y206        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y206        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.407 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg1_reg[9]/Q
                         net (fo=2, routed)           0.816     3.223    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[9]
    SLICE_X48Y246        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.100     3.323 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[9]_i_1/O
                         net (fo=1, routed)           0.059     3.382    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[9]
    SLICE_X48Y246        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.065     2.451    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X48Y246        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.052ns  (logic 0.220ns (20.912%)  route 0.832ns (79.088%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.369ns
    Source Clock Delay      (SCD):    2.329ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.103ns (routing 0.764ns, distribution 1.339ns)
  Clock Net Delay (Destination): 1.983ns (routing 0.960ns, distribution 1.023ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.103     2.329    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X55Y197        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y197        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.408 r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[11]/Q
                         net (fo=2, routed)           0.814     3.222    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[11]
    SLICE_X52Y149        LUT5 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     3.363 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[11]_i_2/O
                         net (fo=1, routed)           0.018     3.381    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[11]
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.983     2.369    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.022ns  (logic 0.178ns (17.418%)  route 0.844ns (82.582%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.369ns
    Source Clock Delay      (SCD):    2.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.107ns (routing 0.764ns, distribution 1.343ns)
  Clock Net Delay (Destination): 1.983ns (routing 0.960ns, distribution 1.023ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.107     2.333    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X55Y199        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y199        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.412 r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[8]/Q
                         net (fo=2, routed)           0.795     3.207    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[8]
    SLICE_X52Y149        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     3.306 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[8]_i_1__0/O
                         net (fo=1, routed)           0.049     3.355    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[8]
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.983     2.369    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.979ns  (logic 0.189ns (19.305%)  route 0.790ns (80.695%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.369ns
    Source Clock Delay      (SCD):    2.329ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.103ns (routing 0.764ns, distribution 1.339ns)
  Clock Net Delay (Destination): 1.983ns (routing 0.960ns, distribution 1.023ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.103     2.329    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X55Y197        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y197        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.408 r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[10]/Q
                         net (fo=2, routed)           0.774     3.182    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[10]
    SLICE_X52Y149        LUT4 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     3.292 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[10]_i_1__0/O
                         net (fo=1, routed)           0.016     3.308    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[10]
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.983     2.369    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X52Y149        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.948ns  (logic 0.225ns (23.733%)  route 0.723ns (76.267%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.376ns
    Source Clock Delay      (SCD):    2.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.105ns (routing 0.764ns, distribution 1.341ns)
  Clock Net Delay (Destination): 1.990ns (routing 0.960ns, distribution 1.030ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.105     2.331    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y193        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y193        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.410 r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg7_reg[0]/Q
                         net (fo=2, routed)           0.674     3.084    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[0]
    SLICE_X52Y148        LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     3.230 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[0]_i_1__0/O
                         net (fo=1, routed)           0.049     3.279    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[0]
    SLICE_X52Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.990     2.376    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X52Y148        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        0.485ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.756ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.151ns (routing 0.414ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.648ns, distribution 0.757ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.151     1.271    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X50Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y219        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.310 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.085     1.395    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X50Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.405     1.756    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X50Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        0.485ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.756ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.151ns (routing 0.414ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.648ns, distribution 0.757ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.151     1.271    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X50Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y219        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.310 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.087     1.397    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X50Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.405     1.756    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X50Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.135ns  (logic 0.040ns (29.630%)  route 0.095ns (70.370%))
  Logic Levels:           0  
  Clock Path Skew:        0.486ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.759ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.153ns (routing 0.414ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.648ns, distribution 0.760ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.153     1.273    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y217        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     1.313 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.095     1.408    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.408     1.759    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.039ns (28.676%)  route 0.097ns (71.324%))
  Logic Levels:           0  
  Clock Path Skew:        0.486ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.759ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.153ns (routing 0.414ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.648ns, distribution 0.760ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.153     1.273    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y217        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.312 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.097     1.409    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.408     1.759    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        0.441ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.734ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.173ns (routing 0.414ns, distribution 0.759ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.648ns, distribution 0.735ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.173     1.293    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y165        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.332 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.090     1.422    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.383     1.734    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.040ns (31.008%)  route 0.089ns (68.992%))
  Logic Levels:           0  
  Clock Path Skew:        0.441ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.734ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.173ns (routing 0.414ns, distribution 0.759ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.648ns, distribution 0.735ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.173     1.293    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y165        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.333 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.089     1.422    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.383     1.734    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.038ns (28.006%)  route 0.098ns (71.994%))
  Logic Levels:           0  
  Clock Path Skew:        0.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.742ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.173ns (routing 0.414ns, distribution 0.759ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.648ns, distribution 0.743ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.173     1.293    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X54Y168        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.331 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.098     1.428    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X56Y167        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.391     1.742    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X56Y167        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.040ns (29.412%)  route 0.096ns (70.588%))
  Logic Levels:           0  
  Clock Path Skew:        0.441ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.734ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.173ns (routing 0.414ns, distribution 0.759ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.648ns, distribution 0.735ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.173     1.293    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y165        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.333 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.096     1.429    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.383     1.734    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y165        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.038ns (23.840%)  route 0.121ns (76.160%))
  Logic Levels:           0  
  Clock Path Skew:        0.481ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.168ns (routing 0.414ns, distribution 0.754ns)
  Clock Net Delay (Destination): 1.417ns (routing 0.648ns, distribution 0.769ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.168     1.288    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X46Y221        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.121     1.447    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X48Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.417     1.768    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X48Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.194ns  (logic 0.039ns (20.103%)  route 0.155ns (79.897%))
  Logic Levels:           0  
  Clock Path Skew:        0.486ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.759ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.153ns (routing 0.414ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.648ns, distribution 0.760ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.153     1.273    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y217        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.312 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.155     1.467    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.408     1.759    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X48Y217        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  RFADC2_CLK

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.173ns  (logic 0.146ns (6.720%)  route 2.027ns (93.280%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.597ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.400ns
    Source Clock Delay      (SCD):    2.997ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.780ns (routing 0.764ns, distribution 1.016ns)
  Clock Net Delay (Destination): 2.014ns (routing 0.960ns, distribution 1.054ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.780     2.997    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X70Y85         FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y85         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     3.073 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=445, routed)         1.720     4.792    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X50Y103        LUT1 (Prop_E5LUT_SLICEL_I0_O)
                                                      0.070     4.862 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.307     5.169    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.014     2.400    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.307ns  (logic 0.080ns (26.053%)  route 0.227ns (73.948%))
  Logic Levels:           0  
  Clock Path Skew:        -0.696ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.398ns
    Source Clock Delay      (SCD):    3.094ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.877ns (routing 0.764ns, distribution 1.113ns)
  Clock Net Delay (Destination): 2.012ns (routing 0.960ns, distribution 1.052ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.877     3.094    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X50Y98         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y98         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.174 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=277, routed)         0.227     3.401    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.012     2.398    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.525ns  (logic 0.079ns (15.048%)  route 0.446ns (84.952%))
  Logic Levels:           0  
  Clock Path Skew:        -0.723ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.385ns
    Source Clock Delay      (SCD):    3.108ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.891ns (routing 0.764ns, distribution 1.127ns)
  Clock Net Delay (Destination): 1.999ns (routing 0.960ns, distribution 1.039ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.891     3.108    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y100        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.187 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.446     3.633    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.999     2.385    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.374ns  (logic 0.081ns (21.658%)  route 0.293ns (78.342%))
  Logic Levels:           0  
  Clock Path Skew:        -0.683ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.389ns
    Source Clock Delay      (SCD):    3.072ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.855ns (routing 0.764ns, distribution 1.091ns)
  Clock Net Delay (Destination): 2.003ns (routing 0.960ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.855     3.072    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.153 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.293     3.446    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.003     2.389    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.353ns  (logic 0.080ns (22.663%)  route 0.273ns (77.337%))
  Logic Levels:           0  
  Clock Path Skew:        -0.687ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.385ns
    Source Clock Delay      (SCD):    3.072ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.855ns (routing 0.764ns, distribution 1.091ns)
  Clock Net Delay (Destination): 1.999ns (routing 0.960ns, distribution 1.039ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.855     3.072    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.152 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.273     3.425    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.999     2.385    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.315ns  (logic 0.079ns (25.079%)  route 0.236ns (74.921%))
  Logic Levels:           0  
  Clock Path Skew:        -0.681ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.391ns
    Source Clock Delay      (SCD):    3.072ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.855ns (routing 0.764ns, distribution 1.091ns)
  Clock Net Delay (Destination): 2.005ns (routing 0.960ns, distribution 1.045ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.855     3.072    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.151 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.236     3.387    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X51Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.005     2.391    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.280ns  (logic 0.079ns (28.214%)  route 0.201ns (71.786%))
  Logic Levels:           0  
  Clock Path Skew:        -0.683ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.389ns
    Source Clock Delay      (SCD):    3.072ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.855ns (routing 0.764ns, distribution 1.091ns)
  Clock Net Delay (Destination): 2.003ns (routing 0.960ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.855     3.072    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.151 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.201     3.352    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.003     2.389    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.748ns
    Source Clock Delay      (SCD):    2.032ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.027ns (routing 0.421ns, distribution 0.606ns)
  Clock Net Delay (Destination): 1.397ns (routing 0.648ns, distribution 0.749ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.027     2.032    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.071 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.081     2.152    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.397     1.748    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.857%)  route 0.101ns (72.143%))
  Logic Levels:           0  
  Clock Path Skew:        -0.279ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    2.032ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.027ns (routing 0.421ns, distribution 0.606ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.648ns, distribution 0.754ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.027     2.032    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.071 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.101     2.172    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X51Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.402     1.753    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.391%)  route 0.098ns (71.609%))
  Logic Levels:           0  
  Clock Path Skew:        -0.287ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.755ns
    Source Clock Delay      (SCD):    2.042ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.037ns (routing 0.421ns, distribution 0.616ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.648ns, distribution 0.756ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.037     2.042    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X50Y98         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y98         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.081 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=277, routed)         0.098     2.179    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.404     1.755    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.039ns (24.841%)  route 0.118ns (75.159%))
  Logic Levels:           0  
  Clock Path Skew:        -0.286ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.746ns
    Source Clock Delay      (SCD):    2.032ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.027ns (routing 0.421ns, distribution 0.606ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.648ns, distribution 0.747ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.027     2.032    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.071 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.118     2.189    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.395     1.746    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.169ns  (logic 0.040ns (23.669%)  route 0.129ns (76.331%))
  Logic Levels:           0  
  Clock Path Skew:        -0.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.748ns
    Source Clock Delay      (SCD):    2.032ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.027ns (routing 0.421ns, distribution 0.606ns)
  Clock Net Delay (Destination): 1.397ns (routing 0.648ns, distribution 0.749ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.027     2.032    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y100        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.072 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.129     2.201    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.397     1.748    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.246ns  (logic 0.039ns (15.854%)  route 0.207ns (84.146%))
  Logic Levels:           0  
  Clock Path Skew:        -0.301ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.746ns
    Source Clock Delay      (SCD):    2.047ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.041ns (routing 0.421ns, distribution 0.620ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.648ns, distribution 0.747ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.041     2.047    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y100        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.086 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.207     2.293    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.395     1.746    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.043ns  (logic 0.057ns (5.465%)  route 0.986ns (94.535%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.230ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.759ns
    Source Clock Delay      (SCD):    1.989ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.984ns (routing 0.421ns, distribution 0.563ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.648ns, distribution 0.760ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.984     1.989    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X70Y85         FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y85         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.026 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=445, routed)         0.846     2.872    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X50Y103        LUT1 (Prop_E5LUT_SLICEL_I0_O)
                                                      0.020     2.892 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.140     3.032    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.408     1.759    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC2_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.966ns  (logic 0.090ns (4.579%)  route 1.876ns (95.421%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 3.053ns (routing 1.690ns, distribution 1.363ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           1.820     1.820    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X79Y115        LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     1.910 r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.056     1.966    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X79Y115        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.053     3.597    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X79Y115        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.938ns  (logic 0.035ns (3.732%)  route 0.903ns (96.268%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.088ns (routing 1.128ns, distribution 0.960ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           0.883     0.883    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X79Y115        LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.035     0.918 r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.020     0.938    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X79Y115        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.088     2.563    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X79Y115        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  RFDAC2_CLK

Max Delay           138 Endpoints
Min Delay           138 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[49]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.876ns  (logic 0.301ns (34.361%)  route 0.575ns (65.639%))
  Logic Levels:           0  
  Clock Path Skew:        0.627ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.800ns
    Source Clock Delay      (SCD):    3.173ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.647ns (routing 1.062ns, distribution 1.585ns)
  Clock Net Delay (Destination): 3.256ns (routing 1.690ns, distribution 1.566ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.647     3.173    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X118Y138       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y138       RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     3.474 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD_D1/O
                         net (fo=1, routed)           0.575     4.049    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[49]
    SLICE_X114Y138       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[49]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.256     3.800    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X114Y138       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[49]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[84]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.848ns  (logic 0.289ns (34.080%)  route 0.559ns (65.920%))
  Logic Levels:           0  
  Clock Path Skew:        0.638ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.808ns
    Source Clock Delay      (SCD):    3.170ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.062ns, distribution 1.582ns)
  Clock Net Delay (Destination): 3.264ns (routing 1.690ns, distribution 1.574ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.644     3.170    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97/WCLK
    SLICE_X118Y141       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y141       RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     3.459 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_97/RAMA/O
                         net (fo=1, routed)           0.559     4.018    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[84]
    SLICE_X115Y135       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[84]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.264     3.808    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X115Y135       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[84]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[115]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.816ns  (logic 0.307ns (37.623%)  route 0.509ns (62.377%))
  Logic Levels:           0  
  Clock Path Skew:        0.624ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.792ns
    Source Clock Delay      (SCD):    3.168ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.642ns (routing 1.062ns, distribution 1.580ns)
  Clock Net Delay (Destination): 3.248ns (routing 1.690ns, distribution 1.558ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.642     3.168    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X118Y143       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y143       RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     3.475 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/O
                         net (fo=1, routed)           0.509     3.984    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[115]
    SLICE_X115Y142       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[115]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.248     3.792    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X115Y142       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[115]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.790ns  (logic 0.289ns (36.582%)  route 0.501ns (63.418%))
  Logic Levels:           0  
  Clock Path Skew:        0.633ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.808ns
    Source Clock Delay      (SCD):    3.175ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.062ns, distribution 1.587ns)
  Clock Net Delay (Destination): 3.264ns (routing 1.690ns, distribution 1.574ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.649     3.175    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X118Y136       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y136       RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     3.464 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA/O
                         net (fo=1, routed)           0.501     3.965    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[14]
    SLICE_X115Y135       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.264     3.808    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X115Y135       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[67]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.793ns  (logic 0.304ns (38.335%)  route 0.489ns (61.665%))
  Logic Levels:           0  
  Clock Path Skew:        0.626ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.798ns
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.062ns, distribution 1.584ns)
  Clock Net Delay (Destination): 3.254ns (routing 1.690ns, distribution 1.564ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.646     3.172    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/WCLK
    SLICE_X118Y139       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y139       RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     3.476 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMF_D1/O
                         net (fo=1, routed)           0.489     3.965    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[67]
    SLICE_X117Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[67]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.254     3.798    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X117Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[67]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[68]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.792ns  (logic 0.281ns (35.480%)  route 0.511ns (64.520%))
  Logic Levels:           0  
  Clock Path Skew:        0.631ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.803ns
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.062ns, distribution 1.584ns)
  Clock Net Delay (Destination): 3.259ns (routing 1.690ns, distribution 1.569ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.646     3.172    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/WCLK
    SLICE_X118Y139       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y139       RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     3.453 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMG/O
                         net (fo=1, routed)           0.511     3.964    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[68]
    SLICE_X118Y131       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[68]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.259     3.803    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X118Y131       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[68]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[100]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.792ns  (logic 0.292ns (36.869%)  route 0.500ns (63.131%))
  Logic Levels:           0  
  Clock Path Skew:        0.627ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.796ns
    Source Clock Delay      (SCD):    3.169ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.643ns (routing 1.062ns, distribution 1.581ns)
  Clock Net Delay (Destination): 3.252ns (routing 1.690ns, distribution 1.562ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.643     3.169    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X118Y142       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y142       RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     3.461 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB/O
                         net (fo=1, routed)           0.500     3.961    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[100]
    SLICE_X118Y140       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[100]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.252     3.796    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X118Y140       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[100]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.786ns  (logic 0.295ns (37.532%)  route 0.491ns (62.468%))
  Logic Levels:           0  
  Clock Path Skew:        0.623ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.796ns
    Source Clock Delay      (SCD):    3.173ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.647ns (routing 1.062ns, distribution 1.585ns)
  Clock Net Delay (Destination): 3.252ns (routing 1.690ns, distribution 1.562ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.647     3.173    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X118Y138       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y138       RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     3.468 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/O
                         net (fo=1, routed)           0.491     3.959    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[55]
    SLICE_X116Y138       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.252     3.796    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X116Y138       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.784ns  (logic 0.289ns (36.862%)  route 0.495ns (63.138%))
  Logic Levels:           0  
  Clock Path Skew:        0.628ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.802ns
    Source Clock Delay      (SCD):    3.174ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.648ns (routing 1.062ns, distribution 1.586ns)
  Clock Net Delay (Destination): 3.258ns (routing 1.690ns, distribution 1.568ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.648     3.174    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X118Y137       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y137       RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     3.463 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/O
                         net (fo=1, routed)           0.495     3.958    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[28]
    SLICE_X116Y137       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.258     3.802    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X116Y137       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[53]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.778ns  (logic 0.304ns (39.075%)  route 0.474ns (60.925%))
  Logic Levels:           0  
  Clock Path Skew:        0.623ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.796ns
    Source Clock Delay      (SCD):    3.173ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.647ns (routing 1.062ns, distribution 1.585ns)
  Clock Net Delay (Destination): 3.252ns (routing 1.690ns, distribution 1.562ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.647     3.173    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X118Y138       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y138       RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     3.477 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMF_D1/O
                         net (fo=1, routed)           0.474     3.951    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[53]
    SLICE_X116Y138       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[53]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.252     3.796    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X116Y138       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[53]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.500%)  route 0.068ns (63.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.987ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.683ns
    Source Clock Delay      (SCD):    1.696ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.434ns (routing 0.578ns, distribution 0.856ns)
  Clock Net Delay (Destination): 2.208ns (routing 1.128ns, distribution 1.080ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.434     1.696    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X115Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y144       FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.735 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.068     1.802    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X115Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.208     2.683    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X115Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.038ns (29.231%)  route 0.092ns (70.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.992ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.684ns
    Source Clock Delay      (SCD):    1.692ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.430ns (routing 0.578ns, distribution 0.852ns)
  Clock Net Delay (Destination): 2.209ns (routing 1.128ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.430     1.692    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X118Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y144       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.730 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.092     1.822    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X118Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.209     2.684    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X118Y144       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.164ns  (logic 0.039ns (23.780%)  route 0.125ns (76.219%))
  Logic Levels:           0  
  Clock Path Skew:        0.987ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.684ns
    Source Clock Delay      (SCD):    1.697ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.435ns (routing 0.578ns, distribution 0.857ns)
  Clock Net Delay (Destination): 2.209ns (routing 1.128ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.435     1.697    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y136       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.736 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.125     1.861    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.209     2.684    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.039ns (23.214%)  route 0.129ns (76.786%))
  Logic Levels:           0  
  Clock Path Skew:        0.995ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.692ns
    Source Clock Delay      (SCD):    1.697ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.435ns (routing 0.578ns, distribution 0.857ns)
  Clock Net Delay (Destination): 2.217ns (routing 1.128ns, distribution 1.089ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.435     1.697    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y136       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.736 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.129     1.865    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X117Y137       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.217     2.692    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X117Y137       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.169ns  (logic 0.040ns (23.669%)  route 0.129ns (76.331%))
  Logic Levels:           0  
  Clock Path Skew:        0.987ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.684ns
    Source Clock Delay      (SCD):    1.697ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.435ns (routing 0.578ns, distribution 0.857ns)
  Clock Net Delay (Destination): 2.209ns (routing 1.128ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.435     1.697    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y136       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.737 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.129     1.866    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.209     2.684    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X117Y136       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.110ns (63.953%)  route 0.062ns (36.047%))
  Logic Levels:           0  
  Clock Path Skew:        0.975ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.694ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.457ns (routing 0.578ns, distribution 0.879ns)
  Clock Net Delay (Destination): 2.219ns (routing 1.128ns, distribution 1.091ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.457     1.719    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X118Y134       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y134       RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     1.829 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/O
                         net (fo=1, routed)           0.062     1.891    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[3]
    SLICE_X118Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.219     2.694    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X118Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.108ns (61.714%)  route 0.067ns (38.286%))
  Logic Levels:           0  
  Clock Path Skew:        0.975ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.694ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.457ns (routing 0.578ns, distribution 0.879ns)
  Clock Net Delay (Destination): 2.219ns (routing 1.128ns, distribution 1.091ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.457     1.719    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X118Y134       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y134       RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     1.827 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAME_D1/O
                         net (fo=1, routed)           0.067     1.894    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[9]
    SLICE_X118Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.219     2.694    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X118Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[75]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.187ns  (logic 0.110ns (58.824%)  route 0.077ns (41.176%))
  Logic Levels:           0  
  Clock Path Skew:        0.976ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.694ns
    Source Clock Delay      (SCD):    1.718ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.456ns (routing 0.578ns, distribution 0.878ns)
  Clock Net Delay (Destination): 2.219ns (routing 1.128ns, distribution 1.091ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.456     1.718    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/WCLK
    SLICE_X118Y135       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y135       RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     1.828 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_70_83/RAMC_D1/O
                         net (fo=1, routed)           0.077     1.905    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[75]
    SLICE_X118Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[75]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.219     2.694    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X118Y133       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[75]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[99]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.191ns  (logic 0.111ns (58.115%)  route 0.080ns (41.885%))
  Logic Levels:           0  
  Clock Path Skew:        0.976ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.691ns
    Source Clock Delay      (SCD):    1.715ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.453ns (routing 0.578ns, distribution 0.875ns)
  Clock Net Delay (Destination): 2.216ns (routing 1.128ns, distribution 1.088ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.453     1.715    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X118Y142       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y142       RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     1.826 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMA_D1/O
                         net (fo=1, routed)           0.080     1.906    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[99]
    SLICE_X118Y140       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[99]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.216     2.691    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X118Y140       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[99]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[63]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.191ns  (logic 0.111ns (58.115%)  route 0.080ns (41.885%))
  Logic Levels:           0  
  Clock Path Skew:        0.970ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.686ns
    Source Clock Delay      (SCD):    1.716ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.454ns (routing 0.578ns, distribution 0.876ns)
  Clock Net Delay (Destination): 2.211ns (routing 1.128ns, distribution 1.083ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.454     1.716    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/WCLK
    SLICE_X118Y139       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y139       RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     1.827 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMD_D1/O
                         net (fo=1, routed)           0.080     1.907    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[63]
    SLICE_X117Y140       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[63]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.211     2.686    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X117Y140       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[63]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  RFDAC2_CLK

Max Delay         37427 Endpoints
Min Delay         37427 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.501ns  (logic 0.203ns (3.691%)  route 5.298ns (96.309%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.573ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.527ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.983ns (routing 1.690ns, distribution 1.293ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.478     7.691    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X37Y190        LUT1 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.096     7.787 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          1.814     9.601    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X26Y182        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.983     3.527    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X26Y182        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_4/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.382ns  (logic 0.230ns (4.274%)  route 5.152ns (95.726%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.339ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.761ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 3.217ns (routing 1.690ns, distribution 1.527ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.145     7.358    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X104Y251       LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     7.481 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=22, routed)          2.001     9.482    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X97Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_4/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.217     3.761    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X97Y277        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_4/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.370ns  (logic 0.250ns (4.655%)  route 5.120ns (95.345%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.430ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.670ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 3.126ns (routing 1.690ns, distribution 1.436ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.174     7.387    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X88Y206        LUT1 (Prop_F5LUT_SLICEL_I0_O)
                                                      0.143     7.530 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=22, routed)          1.940     9.470    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X87Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.126     3.670    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X87Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.359ns  (logic 0.250ns (4.665%)  route 5.109ns (95.335%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.430ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.670ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 3.126ns (routing 1.690ns, distribution 1.436ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.174     7.387    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X88Y206        LUT1 (Prop_F5LUT_SLICEL_I0_O)
                                                      0.143     7.530 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=22, routed)          1.929     9.459    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X87Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.126     3.670    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X87Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.334ns  (logic 0.203ns (3.806%)  route 5.131ns (96.194%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.573ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.527ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.983ns (routing 1.690ns, distribution 1.293ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.478     7.691    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X37Y190        LUT1 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.096     7.787 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          1.647     9.434    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X31Y182        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.983     3.527    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X31Y182        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.156ns  (logic 0.230ns (4.461%)  route 4.926ns (95.539%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.393ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.707ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 3.163ns (routing 1.690ns, distribution 1.473ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.145     7.358    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X104Y251       LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     7.481 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=22, routed)          1.775     9.256    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X96Y276        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.163     3.707    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X96Y276        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_15/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.132ns  (logic 0.203ns (3.955%)  route 4.929ns (96.045%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.588ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.512ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.968ns (routing 1.690ns, distribution 1.278ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.478     7.691    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X37Y190        LUT1 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.096     7.787 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          1.445     9.232    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X37Y172        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_15/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.968     3.512    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X37Y172        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_15/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.127ns  (logic 0.259ns (5.052%)  route 4.868ns (94.948%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.643ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.457ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.913ns (routing 1.690ns, distribution 1.223ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.527     7.740    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X54Y136        LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     7.892 r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=5, routed)           1.335     9.227    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X43Y88         FDRE                                         r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.913     3.457    d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X43Y88         FDRE                                         r  d_1_i/axis_readout_v3_0/inst/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.114ns  (logic 0.230ns (4.497%)  route 4.884ns (95.503%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.800ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 3.256ns (routing 1.690ns, distribution 1.566ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.145     7.358    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X104Y251       LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     7.481 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=22, routed)          1.733     9.214    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X105Y312       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.256     3.800    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X105Y312       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.084ns  (logic 0.250ns (4.918%)  route 4.834ns (95.082%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.455ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.645ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 3.101ns (routing 1.690ns, distribution 1.411ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.174     7.387    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X88Y206        LUT1 (Prop_F5LUT_SLICEL_I0_O)
                                                      0.143     7.530 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=22, routed)          1.654     9.184    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X83Y218        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.101     3.645    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X83Y218        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.459ns  (logic 0.039ns (8.495%)  route 0.420ns (91.505%))
  Logic Levels:           0  
  Clock Path Skew:        0.255ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    2.220ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.853ns (routing 1.007ns, distribution 0.846ns)
  Clock Net Delay (Destination): 2.000ns (routing 1.128ns, distribution 0.872ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.853     2.220    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X77Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y247        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.259 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           0.420     2.679    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X47Y258        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.000     2.475    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X47Y258        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.670ns  (logic 0.056ns (3.353%)  route 1.614ns (96.647%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.566     3.887    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y274        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y274        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/clear_r_reg/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.670ns  (logic 0.056ns (3.353%)  route 1.614ns (96.647%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.566     3.887    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y274        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/clear_r_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y274        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/clear_r_reg/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.670ns  (logic 0.056ns (3.353%)  route 1.614ns (96.647%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.566     3.887    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y274        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y274        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.670ns  (logic 0.056ns (3.353%)  route 1.614ns (96.647%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.566     3.887    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y274        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y274        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.670ns  (logic 0.056ns (3.353%)  route 1.614ns (96.647%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.566     3.887    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y274        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y274        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.673ns  (logic 0.056ns (3.348%)  route 1.617ns (96.652%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.595ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.120ns (routing 1.128ns, distribution 0.992ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.569     3.890    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y273        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.120     2.595    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y273        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[4]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.673ns  (logic 0.056ns (3.348%)  route 1.617ns (96.652%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.595ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.120ns (routing 1.128ns, distribution 0.992ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.569     3.890    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y273        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.120     2.595    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y273        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.673ns  (logic 0.056ns (3.348%)  route 1.617ns (96.652%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.569     3.890    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y273        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y273        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CLR
                            (removal check against rising-edge clock RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        1.673ns  (logic 0.056ns (3.348%)  route 1.617ns (96.652%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 2.124ns (routing 1.128ns, distribution 0.996ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.569     3.890    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]_0
    SLICE_X81Y273        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.124     2.599    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X81Y273        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  RFDAC2_CLK

Max Delay           793 Endpoints
Min Delay           793 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.768ns  (logic 0.625ns (16.587%)  route 3.143ns (83.413%))
  Logic Levels:           8  (LUT3=2 LUT4=1 LUT5=3 LUT6=2)
  Clock Path Skew:        -1.767ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.603ns
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.749ns (routing 1.545ns, distribution 1.204ns)
  Clock Net Delay (Destination): 3.059ns (routing 1.690ns, distribution 1.369ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.749     5.370    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y265        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.451 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/Q
                         net (fo=1, routed)           0.193     5.644    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/out[6]
    SLICE_X91Y265        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.790 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15/O
                         net (fo=3, routed)           0.204     5.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15_n_0
    SLICE_X89Y264        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     6.031 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_32/O
                         net (fo=2, routed)           0.848     6.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][14]_i_15[0]
    SLICE_X78Y250        LUT4 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     7.004 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_15/O
                         net (fo=3, routed)           0.290     7.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg_0
    SLICE_X74Y248        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     7.384 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=3, routed)           0.156     7.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X74Y249        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     7.575 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=593, routed)         0.477     8.052    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X66Y249        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     8.091 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.192     8.283    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][5]_1
    SLICE_X66Y245        LUT3 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.037     8.320 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.269     8.589    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc_reg[3]
    SLICE_X64Y246        LUT3 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     8.624 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1/O
                         net (fo=33, routed)          0.514     9.138    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[3]
    SLICE_X77Y247        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.059     3.603    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X77Y247        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.515ns  (logic 0.643ns (18.295%)  route 2.872ns (81.705%))
  Logic Levels:           7  (LUT4=1 LUT5=3 LUT6=3)
  Clock Path Skew:        -1.757ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.613ns
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.749ns (routing 1.545ns, distribution 1.204ns)
  Clock Net Delay (Destination): 3.069ns (routing 1.690ns, distribution 1.379ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.749     5.370    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y265        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.451 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_r_reg[6]/Q
                         net (fo=1, routed)           0.193     5.644    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/out[6]
    SLICE_X91Y265        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.790 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15/O
                         net (fo=3, routed)           0.204     5.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__15_n_0
    SLICE_X89Y264        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     6.031 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_32/O
                         net (fo=2, routed)           0.848     6.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][14]_i_15[0]
    SLICE_X78Y250        LUT4 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.125     7.004 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_15/O
                         net (fo=3, routed)           0.290     7.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg_0
    SLICE_X74Y248        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     7.384 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=3, routed)           0.156     7.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X74Y249        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     7.575 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=593, routed)         0.477     8.052    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X66Y249        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     8.091 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.313     8.405    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc_reg[4]
    SLICE_X67Y242        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     8.495 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.390     8.885    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X79Y243        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.069     3.613    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X79Y243        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
                            (rising edge-triggered cell FDPE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.525ns  (logic 0.410ns (16.240%)  route 2.115ns (83.760%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.660ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.569ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.025ns (routing 1.690ns, distribution 1.335ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.287     7.754    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.025     3.569    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.525ns  (logic 0.410ns (16.240%)  route 2.115ns (83.760%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.660ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.569ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.025ns (routing 1.690ns, distribution 1.335ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.287     7.754    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.025     3.569    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.523ns  (logic 0.410ns (16.253%)  route 2.113ns (83.747%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.660ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.569ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.025ns (routing 1.690ns, distribution 1.335ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.285     7.752    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.025     3.569    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.523ns  (logic 0.410ns (16.253%)  route 2.113ns (83.747%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.660ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.569ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.025ns (routing 1.690ns, distribution 1.335ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.285     7.752    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.025     3.569    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.499ns  (logic 0.410ns (16.407%)  route 2.089ns (83.593%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.659ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.570ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.026ns (routing 1.690ns, distribution 1.336ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.261     7.728    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.026     3.570    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.499ns  (logic 0.410ns (16.407%)  route 2.089ns (83.593%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.659ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.570ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.026ns (routing 1.690ns, distribution 1.336ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.261     7.728    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.026     3.570    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.499ns  (logic 0.410ns (16.407%)  route 2.089ns (83.593%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.659ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.570ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.026ns (routing 1.690ns, distribution 1.336ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.261     7.728    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.026     3.570    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.499ns  (logic 0.410ns (16.407%)  route 2.089ns (83.593%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.659ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.570ns
    Source Clock Delay      (SCD):    5.229ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.608ns (routing 1.545ns, distribution 1.063ns)
  Clock Net Delay (Destination): 3.026ns (routing 1.690ns, distribution 1.336ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.608     5.229    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X79Y241        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y241        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.305 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           1.271     6.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req
    SLICE_X79Y241        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.159     6.735 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_fifo_trig_empty_inferred_i_12/O
                         net (fo=1, routed)           0.275     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X76Y246        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     7.047 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[1]_i_2/O
                         net (fo=1, routed)           0.047     7.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r_reg[1]
    SLICE_X76Y246        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     7.195 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].ADDSUB_MACRO_inst/trig_pop_r[1]_i_1/O
                         net (fo=2, routed)           0.234     7.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/trig_pop82_out
    SLICE_X79Y241        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     7.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__1/O
                         net (fo=18, routed)          0.261     7.728    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.026     3.570    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.037ns (38.669%)  route 0.059ns (61.331%))
  Logic Levels:           0  
  Clock Path Skew:        -0.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.503ns
    Source Clock Delay      (SCD):    3.142ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.393ns (routing 0.846ns, distribution 0.547ns)
  Clock Net Delay (Destination): 2.028ns (routing 1.128ns, distribution 0.900ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.393     3.142    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y222        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     3.179 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/Q
                         net (fo=2, routed)           0.059     3.237    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr[8]
    SLICE_X68Y222        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.028     2.503    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/t_clk_i
    SLICE_X68Y222        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.077ns  (logic 0.039ns (50.859%)  route 0.038ns (49.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.541ns
    Source Clock Delay      (SCD):    3.163ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.414ns (routing 0.846ns, distribution 0.568ns)
  Clock Net Delay (Destination): 2.066ns (routing 1.128ns, distribution 0.938ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.414     3.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y284        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y284        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.202 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=4, routed)           0.038     3.240    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/wr_gptr[7]
    SLICE_X73Y283        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.066     2.541    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/t_clk_i
    SLICE_X73Y283        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.255%)  route 0.066ns (62.745%))
  Logic Levels:           0  
  Clock Path Skew:        -0.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.500ns
    Source Clock Delay      (SCD):    3.138ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.389ns (routing 0.846ns, distribution 0.543ns)
  Clock Net Delay (Destination): 2.025ns (routing 1.128ns, distribution 0.897ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.389     3.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y223        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y223        FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     3.177 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/Q
                         net (fo=2, routed)           0.066     3.243    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr[5]
    SLICE_X67Y223        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.025     2.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/t_clk_i
    SLICE_X67Y223        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        -0.643ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.502ns
    Source Clock Delay      (SCD):    3.146ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.397ns (routing 0.846ns, distribution 0.551ns)
  Clock Net Delay (Destination): 2.027ns (routing 1.128ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.397     3.146    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y231        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.185 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.059     3.243    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr[3]
    SLICE_X68Y231        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.027     2.502    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_clk_i
    SLICE_X68Y231        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.080%)  route 0.066ns (62.920%))
  Logic Levels:           0  
  Clock Path Skew:        -0.640ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.501ns
    Source Clock Delay      (SCD):    3.142ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.393ns (routing 0.846ns, distribution 0.547ns)
  Clock Net Delay (Destination): 2.026ns (routing 1.128ns, distribution 0.898ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.393     3.142    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y212        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.181 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=4, routed)           0.066     3.247    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/wr_gptr[7]
    SLICE_X73Y212        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.026     2.501    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/t_clk_i
    SLICE_X73Y212        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.903%)  route 0.067ns (63.097%))
  Logic Levels:           0  
  Clock Path Skew:        -0.632ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.510ns
    Source Clock Delay      (SCD):    3.142ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.393ns (routing 0.846ns, distribution 0.547ns)
  Clock Net Delay (Destination): 2.035ns (routing 1.128ns, distribution 0.907ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.393     3.142    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y222        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.181 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.067     3.247    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr[1]
    SLICE_X67Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.035     2.510    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/t_clk_i
    SLICE_X67Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.041ns (38.795%)  route 0.065ns (61.205%))
  Logic Levels:           0  
  Clock Path Skew:        -0.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.510ns
    Source Clock Delay      (SCD):    3.143ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.394ns (routing 0.846ns, distribution 0.548ns)
  Clock Net Delay (Destination): 2.035ns (routing 1.128ns, distribution 0.907ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.394     3.143    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y222        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     3.184 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=2, routed)           0.065     3.248    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr[0]
    SLICE_X67Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.035     2.510    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/t_clk_i
    SLICE_X67Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.207%)  route 0.060ns (60.793%))
  Logic Levels:           0  
  Clock Path Skew:        -0.643ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.506ns
    Source Clock Delay      (SCD):    3.149ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.400ns (routing 0.846ns, distribution 0.554ns)
  Clock Net Delay (Destination): 2.031ns (routing 1.128ns, distribution 0.903ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.400     3.149    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X68Y229        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y229        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.188 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/Q
                         net (fo=2, routed)           0.060     3.249    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr[4]
    SLICE_X68Y231        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.031     2.506    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_clk_i
    SLICE_X68Y231        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.617%)  route 0.059ns (60.383%))
  Logic Levels:           0  
  Clock Path Skew:        -0.632ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    3.155ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.406ns (routing 0.846ns, distribution 0.560ns)
  Clock Net Delay (Destination): 2.047ns (routing 1.128ns, distribution 0.919ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.406     3.155    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X77Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y234        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     3.194 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.059     3.253    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[7]
    SLICE_X77Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.047     2.522    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X77Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.111ns  (logic 0.039ns (35.236%)  route 0.072ns (64.764%))
  Logic Levels:           0  
  Clock Path Skew:        -0.631ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.512ns
    Source Clock Delay      (SCD):    3.143ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.394ns (routing 0.846ns, distribution 0.548ns)
  Clock Net Delay (Destination): 2.037ns (routing 1.128ns, distribution 0.909ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.394     3.143    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X67Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y222        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.182 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.072     3.253    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr[2]
    SLICE_X67Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.037     2.512    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/t_clk_i
    SLICE_X67Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[12].trig_fifo_inst/wr_gptr_cdc_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC2_CLK

Max Delay           207 Endpoints
Min Delay           207 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.404ns  (logic 0.079ns (5.627%)  route 1.325ns (94.373%))
  Logic Levels:           0  
  Clock Path Skew:        1.130ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.851ns
    Source Clock Delay      (SCD):    2.721ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.495ns (routing 0.764ns, distribution 1.731ns)
  Clock Net Delay (Destination): 3.307ns (routing 1.690ns, distribution 1.617ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.495     2.721    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y198       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.800 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/Q
                         net (fo=1, routed)           1.325     4.125    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/src_in
    SLICE_X116Y309       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.307     3.851    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/dest_clk
    SLICE_X116Y309       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.201ns  (logic 0.078ns (6.495%)  route 1.123ns (93.505%))
  Logic Levels:           0  
  Clock Path Skew:        1.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.832ns
    Source Clock Delay      (SCD):    2.760ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.534ns (routing 0.764ns, distribution 1.770ns)
  Clock Net Delay (Destination): 3.288ns (routing 1.690ns, distribution 1.598ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.534     2.760    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y191       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.838 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           1.123     3.961    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X115Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.288     3.832    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X115Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.651ns  (logic 0.078ns (11.982%)  route 0.573ns (88.018%))
  Logic Levels:           0  
  Clock Path Skew:        1.021ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.784ns
    Source Clock Delay      (SCD):    2.763ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.537ns (routing 0.764ns, distribution 1.773ns)
  Clock Net Delay (Destination): 3.240ns (routing 1.690ns, distribution 1.550ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.537     2.763    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X110Y196       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y196       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.573     3.414    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X116Y236       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.240     3.784    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X116Y236       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_4/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.539ns  (logic 0.191ns (7.522%)  route 2.348ns (92.478%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        1.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.600ns
    Source Clock Delay      (SCD):    2.516ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.290ns (routing 0.764ns, distribution 1.526ns)
  Clock Net Delay (Destination): 3.056ns (routing 1.690ns, distribution 1.366ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.290     2.516    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y261        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y261        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.597 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.393     3.989    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X25Y382        LUT4 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     4.099 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=10, routed)          0.956     5.055    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[1]
    SLICE_X29Y442        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_4/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.056     3.600    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X29Y442        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_4/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_5/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.486ns  (logic 0.191ns (7.682%)  route 2.295ns (92.318%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        1.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.608ns
    Source Clock Delay      (SCD):    2.516ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.290ns (routing 0.764ns, distribution 1.526ns)
  Clock Net Delay (Destination): 3.064ns (routing 1.690ns, distribution 1.374ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.290     2.516    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y261        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y261        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.597 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.393     3.989    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X25Y382        LUT4 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     4.099 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=10, routed)          0.903     5.002    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[1]
    SLICE_X31Y432        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_5/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.064     3.608    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X31Y432        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_5/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.470ns  (logic 0.225ns (9.108%)  route 2.245ns (90.892%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        1.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.593ns
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.764ns, distribution 1.522ns)
  Clock Net Delay (Destination): 3.049ns (routing 1.690ns, distribution 1.359ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.286     2.512    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y264        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y264        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.591 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/Q
                         net (fo=2, routed)           1.613     4.204    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[12]
    SLICE_X26Y393        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     4.350 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[12]_i_1/O
                         net (fo=8, routed)           0.632     4.982    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[12]
    SLICE_X25Y373        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.049     3.593    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X25Y373        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica_1/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.434ns  (logic 0.225ns (9.243%)  route 2.209ns (90.757%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        1.140ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.652ns
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.764ns, distribution 1.522ns)
  Clock Net Delay (Destination): 3.108ns (routing 1.690ns, distribution 1.418ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.286     2.512    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y264        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y264        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.591 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/Q
                         net (fo=2, routed)           1.613     4.204    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[12]
    SLICE_X26Y393        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     4.350 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[12]_i_1/O
                         net (fo=8, routed)           0.596     4.946    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[12]
    SLICE_X19Y378        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.108     3.652    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X19Y378        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[7]_replica_6/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.423ns  (logic 0.230ns (9.494%)  route 2.193ns (90.506%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        1.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.598ns
    Source Clock Delay      (SCD):    2.516ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.290ns (routing 0.764ns, distribution 1.526ns)
  Clock Net Delay (Destination): 3.054ns (routing 1.690ns, distribution 1.364ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.290     2.516    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y261        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y261        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.596 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[7]/Q
                         net (fo=2, routed)           1.180     3.776    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[7]
    SLICE_X23Y378        LUT5 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     3.926 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[7]_i_1/O
                         net (fo=10, routed)          1.013     4.938    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[7]
    SLICE_X29Y442        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[7]_replica_6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.054     3.598    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X29Y442        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[7]_replica_6/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica_3/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.411ns  (logic 0.225ns (9.334%)  route 2.186ns (90.666%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        1.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.603ns
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.764ns, distribution 1.522ns)
  Clock Net Delay (Destination): 3.059ns (routing 1.690ns, distribution 1.369ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.286     2.512    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y264        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y264        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.591 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/Q
                         net (fo=2, routed)           1.613     4.204    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[12]
    SLICE_X26Y393        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     4.350 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[12]_i_1/O
                         net (fo=8, routed)           0.572     4.922    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[12]
    SLICE_X21Y370        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.059     3.603    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X21Y370        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica_3/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[11]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.402ns  (logic 0.180ns (7.492%)  route 2.222ns (92.508%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        1.128ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.640ns
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.764ns, distribution 1.522ns)
  Clock Net Delay (Destination): 3.096ns (routing 1.690ns, distribution 1.406ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.286     2.512    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y264        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y264        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.593 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[11]/Q
                         net (fo=2, routed)           1.388     3.981    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[11]
    SLICE_X26Y393        LUT4 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     4.080 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[11]_i_1__0/O
                         net (fo=6, routed)           0.834     4.914    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[11]
    SLICE_X19Y358        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[11]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.096     3.640    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X19Y358        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[11]_replica_1/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.310ns  (logic 0.039ns (12.581%)  route 0.271ns (87.419%))
  Logic Levels:           0  
  Clock Path Skew:        1.172ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.673ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.382ns (routing 0.414ns, distribution 0.968ns)
  Clock Net Delay (Destination): 2.198ns (routing 1.128ns, distribution 1.070ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.382     1.502    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X110Y196       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y196       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.541 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.271     1.812    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X116Y236       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.198     2.673    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X116Y236       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.597ns  (logic 0.039ns (6.533%)  route 0.558ns (93.467%))
  Logic Levels:           0  
  Clock Path Skew:        1.208ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.710ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.382ns (routing 0.414ns, distribution 0.968ns)
  Clock Net Delay (Destination): 2.235ns (routing 1.128ns, distribution 1.107ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.382     1.502    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y191       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.541 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.558     2.099    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X115Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.235     2.710    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X115Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.703ns  (logic 0.039ns (5.548%)  route 0.664ns (94.452%))
  Logic Levels:           0  
  Clock Path Skew:        1.239ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.725ns
    Source Clock Delay      (SCD):    1.486ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.366ns (routing 0.414ns, distribution 0.952ns)
  Clock Net Delay (Destination): 2.250ns (routing 1.128ns, distribution 1.122ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.366     1.486    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y198       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/Q
                         net (fo=1, routed)           0.664     2.189    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/src_in
    SLICE_X116Y309       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.250     2.725    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/dest_clk
    SLICE_X116Y309       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg14_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/l_thrsh_r_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.088ns  (logic 0.039ns (44.478%)  route 0.049ns (55.522%))
  Logic Levels:           0  
  Clock Path Skew:        1.159ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.519ns
    Source Clock Delay      (SCD):    1.360ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.240ns (routing 0.414ns, distribution 0.826ns)
  Clock Net Delay (Destination): 2.044ns (routing 1.128ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.240     1.360    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg14_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y262        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.399 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg14_reg[10]/Q
                         net (fo=2, routed)           0.049     1.448    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/l_thrsh_r_reg[15]_0[10]
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/l_thrsh_r_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.044     2.519    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/l_thrsh_r_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.041ns (39.929%)  route 0.062ns (60.071%))
  Logic Levels:           0  
  Clock Path Skew:        1.160ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.519ns
    Source Clock Delay      (SCD):    1.359ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.239ns (routing 0.414ns, distribution 0.825ns)
  Clock Net Delay (Destination): 2.044ns (routing 1.128ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.239     1.359    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y263        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y263        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.400 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[9]/Q
                         net (fo=2, routed)           0.062     1.462    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]_0[9]
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.044     2.519    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.039ns (35.557%)  route 0.071ns (64.443%))
  Logic Levels:           0  
  Clock Path Skew:        1.160ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.519ns
    Source Clock Delay      (SCD):    1.359ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.239ns (routing 0.414ns, distribution 0.825ns)
  Clock Net Delay (Destination): 2.044ns (routing 1.128ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.239     1.359    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y263        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y263        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.398 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[8]/Q
                         net (fo=2, routed)           0.071     1.469    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]_0[8]
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.044     2.519    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X32Y262        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.038ns (35.289%)  route 0.070ns (64.711%))
  Logic Levels:           0  
  Clock Path Skew:        1.149ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 2.047ns (routing 1.128ns, distribution 0.919ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.253     1.373    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X31Y261        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y261        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.411 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[4]/Q
                         net (fo=2, routed)           0.070     1.481    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]_0[4]
    SLICE_X31Y261        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.047     2.522    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X31Y261        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.040ns (32.437%)  route 0.083ns (67.563%))
  Logic Levels:           0  
  Clock Path Skew:        1.159ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.518ns
    Source Clock Delay      (SCD):    1.359ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.239ns (routing 0.414ns, distribution 0.825ns)
  Clock Net Delay (Destination): 2.043ns (routing 1.128ns, distribution 0.915ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.239     1.359    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X32Y263        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y263        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.399 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg13_reg[15]/Q
                         net (fo=2, routed)           0.083     1.482    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]_0[15]
    SLICE_X32Y263        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.043     2.518    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X32Y263        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/h_thrsh_r_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.961%)  route 0.067ns (63.039%))
  Logic Levels:           0  
  Clock Path Skew:        1.154ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.534ns
    Source Clock Delay      (SCD):    1.380ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.260ns (routing 0.414ns, distribution 0.846ns)
  Clock Net Delay (Destination): 2.059ns (routing 1.128ns, distribution 0.931ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.260     1.380    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X32Y342        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y342        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.419 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=74, routed)          0.067     1.485    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]_0[1]
    SLICE_X32Y341        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.059     2.534    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X32Y341        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg8_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/buffer_top_i/buffer_i/len_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.037ns (29.439%)  route 0.089ns (70.561%))
  Logic Levels:           0  
  Clock Path Skew:        1.161ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.521ns
    Source Clock Delay      (SCD):    1.360ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.240ns (routing 0.414ns, distribution 0.826ns)
  Clock Net Delay (Destination): 2.046ns (routing 1.128ns, distribution 0.918ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.240     1.360    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X34Y258        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg8_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y258        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.397 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg8_reg[2]/Q
                         net (fo=2, routed)           0.089     1.486    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/buffer_top_i/buffer_i/len_r_reg[11]_0[2]
    SLICE_X35Y258        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/buffer_top_i/buffer_i/len_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.046     2.521    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X35Y258        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/buffer_top_i/buffer_i/len_r_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           293 Endpoints
Min Delay           293 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.231ns  (logic 0.078ns (6.336%)  route 1.153ns (93.664%))
  Logic Levels:           0  
  Clock Path Skew:        1.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.358ns
    Source Clock Delay      (SCD):    4.074ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.363ns (routing 1.864ns, distribution 1.499ns)
  Clock Net Delay (Destination): 2.283ns (routing 1.400ns, distribution 0.883ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.363     4.074    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X76Y238        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y238        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.152 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=3, routed)           1.153     5.305    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr[0]
    SLICE_X77Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.283     5.358    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X77Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.850ns  (logic 0.078ns (9.180%)  route 0.772ns (90.820%))
  Logic Levels:           0  
  Clock Path Skew:        1.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.516ns
    Source Clock Delay      (SCD):    4.223ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.512ns (routing 1.864ns, distribution 1.648ns)
  Clock Net Delay (Destination): 2.441ns (routing 1.400ns, distribution 1.041ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.512     4.223    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X86Y265        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y265        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.301 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=5, routed)           0.772     5.073    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr[6]
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.441     5.516    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X91Y265        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.992ns  (logic 0.079ns (7.967%)  route 0.913ns (92.034%))
  Logic Levels:           0  
  Clock Path Skew:        1.287ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.336ns
    Source Clock Delay      (SCD):    4.049ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.338ns (routing 1.864ns, distribution 1.474ns)
  Clock Net Delay (Destination): 2.261ns (routing 1.400ns, distribution 0.861ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.338     4.049    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X73Y225        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y225        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.128 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=5, routed)           0.913     5.041    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr[7]
    SLICE_X70Y214        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.261     5.336    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X70Y214        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.769ns  (logic 0.078ns (10.142%)  route 0.691ns (89.858%))
  Logic Levels:           0  
  Clock Path Skew:        1.242ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.479ns
    Source Clock Delay      (SCD):    4.237ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.526ns (routing 1.864ns, distribution 1.662ns)
  Clock Net Delay (Destination): 2.404ns (routing 1.400ns, distribution 1.004ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.526     4.237    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X83Y263        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y263        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.315 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=5, routed)           0.691     5.006    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr[3]
    SLICE_X84Y272        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.404     5.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X84Y272        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.790ns  (logic 0.078ns (9.875%)  route 0.712ns (90.125%))
  Logic Levels:           0  
  Clock Path Skew:        1.269ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.481ns
    Source Clock Delay      (SCD):    4.211ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.500ns (routing 1.864ns, distribution 1.636ns)
  Clock Net Delay (Destination): 2.406ns (routing 1.400ns, distribution 1.006ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.500     4.211    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X83Y265        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y265        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.289 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           0.712     5.001    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr[5]
    SLICE_X84Y272        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.406     5.481    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X84Y272        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/clr_fifo_ack_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.785ns  (logic 0.179ns (22.813%)  route 0.606ns (77.187%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        1.270ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.344ns
    Source Clock Delay      (SCD):    4.074ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.363ns (routing 1.864ns, distribution 1.499ns)
  Clock Net Delay (Destination): 2.269ns (routing 1.400ns, distribution 0.869ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.363     4.074    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X78Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y230        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     4.154 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.557     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/out
    SLICE_X74Y230        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     4.810 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/clr_fifo_ack_i_1__6/O
                         net (fo=1, routed)           0.049     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr_n_4
    SLICE_X74Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/clr_fifo_ack_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.269     5.344    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/c_clk_i
    SLICE_X74Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/clr_fifo_ack_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.762ns  (logic 0.078ns (10.230%)  route 0.684ns (89.770%))
  Logic Levels:           0  
  Clock Path Skew:        1.313ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.401ns
    Source Clock Delay      (SCD):    4.088ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.377ns (routing 1.864ns, distribution 1.513ns)
  Clock Net Delay (Destination): 2.326ns (routing 1.400ns, distribution 0.926ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.377     4.088    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X79Y237        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y237        FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.166 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=3, routed)           0.684     4.850    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr[7]
    SLICE_X76Y241        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.326     5.401    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X76Y241        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.637ns  (logic 0.076ns (11.928%)  route 0.561ns (88.072%))
  Logic Levels:           0  
  Clock Path Skew:        1.268ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.479ns
    Source Clock Delay      (SCD):    4.210ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.499ns (routing 1.864ns, distribution 1.635ns)
  Clock Net Delay (Destination): 2.404ns (routing 1.400ns, distribution 1.004ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.499     4.210    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X83Y265        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y265        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     4.286 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=5, routed)           0.561     4.847    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr[4]
    SLICE_X84Y272        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.404     5.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X84Y272        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.591ns  (logic 0.078ns (13.202%)  route 0.513ns (86.798%))
  Logic Levels:           0  
  Clock Path Skew:        1.256ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.491ns
    Source Clock Delay      (SCD):    4.235ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.524ns (routing 1.864ns, distribution 1.660ns)
  Clock Net Delay (Destination): 2.416ns (routing 1.400ns, distribution 1.016ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.524     4.235    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X83Y264        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y264        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.313 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=5, routed)           0.513     4.826    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr[7]
    SLICE_X83Y271        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.416     5.491    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X83Y271        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.572ns  (logic 0.079ns (13.822%)  route 0.493ns (86.178%))
  Logic Levels:           0  
  Clock Path Skew:        1.278ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.511ns
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.522ns (routing 1.864ns, distribution 1.658ns)
  Clock Net Delay (Destination): 2.436ns (routing 1.400ns, distribution 1.036ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.522     4.233    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X88Y264        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y264        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.312 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           0.493     4.804    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr[5]
    SLICE_X90Y263        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.436     5.511    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X90Y263        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[5]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_req_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_ack_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.039ns (36.217%)  route 0.069ns (63.783%))
  Logic Levels:           0  
  Clock Path Skew:        0.925ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.050ns
    Source Clock Delay      (SCD):    2.125ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.758ns (routing 1.007ns, distribution 0.751ns)
  Clock Net Delay (Destination): 1.628ns (routing 0.950ns, distribution 0.678ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.758     2.125    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/t_clk_i
    SLICE_X58Y234        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y234        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.164 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_req_reg/Q
                         net (fo=3, routed)           0.069     2.233    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_req
    SLICE_X59Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_ack_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.628     3.050    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/c_clk_i
    SLICE_X59Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/b_pulse_ack_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        0.924ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.071ns
    Source Clock Delay      (SCD):    2.147ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.780ns (routing 1.007ns, distribution 0.773ns)
  Clock Net Delay (Destination): 1.649ns (routing 0.950ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.780     2.147    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y242        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.186 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[27]/Q
                         net (fo=1, routed)           0.060     2.246    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[27]
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.649     3.071    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[27]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.039ns (35.337%)  route 0.071ns (64.663%))
  Logic Levels:           0  
  Clock Path Skew:        0.929ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.082ns
    Source Clock Delay      (SCD):    2.153ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.786ns (routing 1.007ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.660ns (routing 0.950ns, distribution 0.710ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.786     2.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X55Y242        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y242        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.192 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=3, routed)           0.071     2.263    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr[7]
    SLICE_X56Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.660     3.082    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X56Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.924ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.071ns
    Source Clock Delay      (SCD):    2.147ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.780ns (routing 1.007ns, distribution 0.773ns)
  Clock Net Delay (Destination): 1.649ns (routing 0.950ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.780     2.147    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y242        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     2.187 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[6]/Q
                         net (fo=1, routed)           0.081     2.268    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[6]
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.649     3.071    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        0.846ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    2.158ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.791ns (routing 1.007ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.582ns (routing 0.950ns, distribution 0.632ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.791     2.158    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y238        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.198 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[14]/Q
                         net (fo=1, routed)           0.078     2.276    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[14]
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.582     3.004    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.786%)  route 0.088ns (69.215%))
  Logic Levels:           0  
  Clock Path Skew:        0.927ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.076ns
    Source Clock Delay      (SCD):    2.150ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.783ns (routing 1.007ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.654ns (routing 0.950ns, distribution 0.704ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.783     2.150    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X57Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y247        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.189 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=3, routed)           0.088     2.276    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr[1]
    SLICE_X57Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.654     3.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X57Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.040ns (30.534%)  route 0.091ns (69.466%))
  Logic Levels:           0  
  Clock Path Skew:        0.924ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.071ns
    Source Clock Delay      (SCD):    2.147ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.780ns (routing 1.007ns, distribution 0.773ns)
  Clock Net Delay (Destination): 1.649ns (routing 0.950ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.780     2.147    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y242        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.187 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[12]/Q
                         net (fo=1, routed)           0.091     2.278    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[12]
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.649     3.071    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X59Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.040ns (30.920%)  route 0.089ns (69.080%))
  Logic Levels:           0  
  Clock Path Skew:        0.927ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.076ns
    Source Clock Delay      (SCD):    2.150ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.783ns (routing 1.007ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.654ns (routing 0.950ns, distribution 0.704ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.783     2.150    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X57Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y247        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     2.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=3, routed)           0.089     2.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr[0]
    SLICE_X57Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.654     3.076    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X57Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.846ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    2.158ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.791ns (routing 1.007ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.582ns (routing 0.950ns, distribution 0.632ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.791     2.158    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y238        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     2.198 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[8]/Q
                         net (fo=1, routed)           0.081     2.279    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[8]
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.582     3.004    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        0.846ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    2.158ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.791ns (routing 1.007ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.582ns (routing 0.950ns, distribution 0.632ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.791     2.158    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y238        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.197 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[10]/Q
                         net (fo=1, routed)           0.086     2.283    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[10]
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.582     3.004    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X62Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[10]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           425 Endpoints
Min Delay           425 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/PR_OUT_DFF[0].FDRE_PER/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.909ns  (logic 0.079ns (4.138%)  route 1.830ns (95.862%))
  Logic Levels:           0  
  Clock Path Skew:        2.899ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.491ns
    Source Clock Delay      (SCD):    2.592ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.366ns (routing 0.764ns, distribution 1.602ns)
  Clock Net Delay (Destination): 2.416ns (routing 1.400ns, distribution 1.016ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.366     2.592    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/PR_OUT_DFF[0].FDRE_PER/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.671 r  d_1_i/rst_100/U0/PR_OUT_DFF[0].FDRE_PER/Q
                         net (fo=2, routed)           1.830     4.501    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X82Y327        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.416     5.491    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X82Y327        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.104ns  (logic 0.287ns (25.996%)  route 0.817ns (74.004%))
  Logic Levels:           0  
  Clock Path Skew:        3.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.475ns
    Source Clock Delay      (SCD):    2.438ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.212ns (routing 0.764ns, distribution 1.448ns)
  Clock Net Delay (Destination): 2.400ns (routing 1.400ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.212     2.438    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X46Y333        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y333        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.725 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/O
                         net (fo=1, routed)           0.817     3.542    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[34]
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.400     5.475    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.069ns  (logic 0.289ns (27.035%)  route 0.780ns (72.965%))
  Logic Levels:           0  
  Clock Path Skew:        3.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.469ns
    Source Clock Delay      (SCD):    2.432ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.206ns (routing 0.764ns, distribution 1.442ns)
  Clock Net Delay (Destination): 2.394ns (routing 1.400ns, distribution 0.994ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.206     2.432    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X48Y278        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y278        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     2.721 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/O
                         net (fo=1, routed)           0.780     3.501    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[0]
    SLICE_X51Y279        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.394     5.469    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X51Y279        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.975ns  (logic 0.307ns (31.487%)  route 0.668ns (68.513%))
  Logic Levels:           0  
  Clock Path Skew:        3.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.475ns
    Source Clock Delay      (SCD):    2.438ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.212ns (routing 0.764ns, distribution 1.448ns)
  Clock Net Delay (Destination): 2.400ns (routing 1.400ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.212     2.438    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X46Y333        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y333        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     2.745 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB_D1/O
                         net (fo=1, routed)           0.668     3.413    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[31]
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.400     5.475    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.958ns  (logic 0.295ns (30.793%)  route 0.663ns (69.207%))
  Logic Levels:           0  
  Clock Path Skew:        3.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.465ns
    Source Clock Delay      (SCD):    2.435ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.209ns (routing 0.764ns, distribution 1.445ns)
  Clock Net Delay (Destination): 2.390ns (routing 1.400ns, distribution 0.990ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.209     2.435    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X46Y331        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y331        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     2.730 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMF/O
                         net (fo=1, routed)           0.663     3.393    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[10]
    SLICE_X54Y320        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.390     5.465    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y320        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.936ns  (logic 0.307ns (32.799%)  route 0.629ns (67.201%))
  Logic Levels:           0  
  Clock Path Skew:        3.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.471ns
    Source Clock Delay      (SCD):    2.438ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.212ns (routing 0.764ns, distribution 1.448ns)
  Clock Net Delay (Destination): 2.396ns (routing 1.400ns, distribution 0.996ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.212     2.438    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X46Y333        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y333        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     2.745 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/O
                         net (fo=1, routed)           0.629     3.374    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[33]
    SLICE_X52Y324        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.396     5.471    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y324        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.949ns  (logic 0.305ns (32.139%)  route 0.644ns (67.861%))
  Logic Levels:           0  
  Clock Path Skew:        3.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.475ns
    Source Clock Delay      (SCD):    2.420ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.194ns (routing 0.764ns, distribution 1.430ns)
  Clock Net Delay (Destination): 2.400ns (routing 1.400ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.194     2.420    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X48Y331        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y331        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     2.725 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA_D1/O
                         net (fo=1, routed)           0.644     3.369    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[15]
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.400     5.475    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[47]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.957ns  (logic 0.307ns (32.079%)  route 0.650ns (67.921%))
  Logic Levels:           0  
  Clock Path Skew:        3.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.481ns
    Source Clock Delay      (SCD):    2.411ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.185ns (routing 0.764ns, distribution 1.421ns)
  Clock Net Delay (Destination): 2.406ns (routing 1.400ns, distribution 1.006ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.185     2.411    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X48Y279        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y279        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     2.718 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/O
                         net (fo=1, routed)           0.650     3.368    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[47]
    SLICE_X48Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.406     5.481    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X48Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[47]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.908ns  (logic 0.292ns (32.159%)  route 0.616ns (67.841%))
  Logic Levels:           0  
  Clock Path Skew:        3.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.465ns
    Source Clock Delay      (SCD):    2.446ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.220ns (routing 0.764ns, distribution 1.456ns)
  Clock Net Delay (Destination): 2.390ns (routing 1.400ns, distribution 0.990ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.220     2.446    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X48Y333        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y333        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     2.738 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB/O
                         net (fo=1, routed)           0.616     3.354    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[58]
    SLICE_X54Y320        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.390     5.465    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y320        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.912ns  (logic 0.288ns (31.579%)  route 0.624ns (68.421%))
  Logic Levels:           0  
  Clock Path Skew:        3.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.475ns
    Source Clock Delay      (SCD):    2.420ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.194ns (routing 0.764ns, distribution 1.430ns)
  Clock Net Delay (Destination): 2.400ns (routing 1.400ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.194     2.420    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X48Y331        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y331        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     2.708 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAME/O
                         net (fo=1, routed)           0.624     3.332    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[22]
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.400     5.475    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X54Y319        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[22]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.040ns (40.404%)  route 0.059ns (59.596%))
  Logic Levels:           0  
  Clock Path Skew:        1.780ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.056ns
    Source Clock Delay      (SCD):    1.276ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.156ns (routing 0.414ns, distribution 0.742ns)
  Clock Net Delay (Destination): 1.634ns (routing 0.950ns, distribution 0.684ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.156     1.276    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y230        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.316 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.059     1.375    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X51Y228        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.634     3.056    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y228        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.351%)  route 0.109ns (73.649%))
  Logic Levels:           0  
  Clock Path Skew:        1.788ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.061ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.153ns (routing 0.414ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.639ns (routing 0.950ns, distribution 0.689ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.153     1.273    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y232        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.312 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.109     1.421    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.639     3.061    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.041ns (33.065%)  route 0.083ns (66.936%))
  Logic Levels:           0  
  Clock Path Skew:        1.780ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.297ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.177ns (routing 0.414ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.655ns (routing 0.950ns, distribution 0.705ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.177     1.297    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X53Y279        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y279        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.338 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.083     1.421    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X52Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.655     3.077    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X52Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        1.780ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.297ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.177ns (routing 0.414ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.655ns (routing 0.950ns, distribution 0.705ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.177     1.297    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X53Y279        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y279        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.336 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.086     1.422    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X52Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.655     3.077    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X52Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.041ns (33.333%)  route 0.082ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        1.788ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.095ns
    Source Clock Delay      (SCD):    1.307ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.187ns (routing 0.414ns, distribution 0.773ns)
  Clock Net Delay (Destination): 1.673ns (routing 0.950ns, distribution 0.723ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.187     1.307    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X48Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y330        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.348 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.082     1.430    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X49Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.673     3.095    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X49Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.279%)  route 0.086ns (68.721%))
  Logic Levels:           0  
  Clock Path Skew:        1.780ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.089ns
    Source Clock Delay      (SCD):    1.310ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.190ns (routing 0.414ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.667ns (routing 0.950ns, distribution 0.717ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.190     1.310    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X49Y283        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y283        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.349 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.086     1.434    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X49Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.667     3.089    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X49Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.786%)  route 0.088ns (69.215%))
  Logic Levels:           0  
  Clock Path Skew:        1.783ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.093ns
    Source Clock Delay      (SCD):    1.310ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.190ns (routing 0.414ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.671ns (routing 0.950ns, distribution 0.721ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.190     1.310    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X49Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y333        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.349 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.088     1.437    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X49Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.671     3.093    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X49Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        1.788ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.081ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.173ns (routing 0.414ns, distribution 0.759ns)
  Clock Net Delay (Destination): 1.659ns (routing 0.950ns, distribution 0.709ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.173     1.293    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y278        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.332 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.107     1.439    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X51Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.659     3.081    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.039ns (23.214%)  route 0.129ns (76.786%))
  Logic Levels:           0  
  Clock Path Skew:        1.789ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.065ns
    Source Clock Delay      (SCD):    1.276ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.156ns (routing 0.414ns, distribution 0.742ns)
  Clock Net Delay (Destination): 1.643ns (routing 0.950ns, distribution 0.693ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.156     1.276    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y230        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.315 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.129     1.444    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.643     3.065    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.143ns  (logic 0.041ns (28.671%)  route 0.102ns (71.329%))
  Logic Levels:           0  
  Clock Path Skew:        1.782ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.090ns
    Source Clock Delay      (SCD):    1.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.188ns (routing 0.414ns, distribution 0.774ns)
  Clock Net Delay (Destination): 1.668ns (routing 0.950ns, distribution 0.718ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.188     1.308    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X47Y331        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y331        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.349 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.102     1.451    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X50Y331        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.668     3.090    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X50Y331        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay           144 Endpoints
Min Delay           144 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.507ns  (logic 0.000ns (0.000%)  route 3.507ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           3.507     3.507    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/src_in
    SLICE_X117Y190       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/dest_clk
    SLICE_X117Y190       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.776ns  (logic 0.000ns (0.000%)  route 2.776ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.246ns (routing 0.691ns, distribution 1.555ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           2.776     2.776    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/src_in
    SLICE_X112Y197       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.246     2.428    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/dest_clk
    SLICE_X112Y197       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.769ns  (logic 0.000ns (0.000%)  route 2.769ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.232ns (routing 0.691ns, distribution 1.541ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.769     2.769    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/src_in
    SLICE_X109Y217       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.232     2.414    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/dest_clk
    SLICE_X109Y217       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.582ns  (logic 0.000ns (0.000%)  route 2.582ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.244ns (routing 0.691ns, distribution 1.553ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[14]
                         net (fo=1, routed)           2.582     2.582    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/src_in
    SLICE_X109Y195       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.244     2.426    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/dest_clk
    SLICE_X109Y195       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.506ns  (logic 0.000ns (0.000%)  route 2.506ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.691ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[15]
                         net (fo=1, routed)           2.506     2.506    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/src_in
    SLICE_X112Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/dest_clk
    SLICE_X112Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.483ns  (logic 0.000ns (0.000%)  route 2.483ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC0[14]
                         net (fo=1, routed)           2.483     2.483    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/src_in
    SLICE_X110Y209       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/dest_clk
    SLICE_X110Y209       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac22_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.386ns  (logic 0.000ns (0.000%)  route 2.386ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.205ns (routing 0.691ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_DAC2[15]
                         net (fo=1, routed)           2.386     2.386    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac22_fifo_irq/src_in
    SLICE_X106Y197       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac22_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.205     2.387    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac22_fifo_irq/dest_clk
    SLICE_X106Y197       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac22_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.382ns  (logic 0.000ns (0.000%)  route 2.382ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.218ns (routing 0.691ns, distribution 1.527ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.382     2.382    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/src_in
    SLICE_X108Y210       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.218     2.400    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/dest_clk
    SLICE_X108Y210       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.355ns  (logic 0.000ns (0.000%)  route 2.355ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.235ns (routing 0.691ns, distribution 1.544ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[15]
                         net (fo=1, routed)           2.355     2.355    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/src_in
    SLICE_X108Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.235     2.417    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/dest_clk
    SLICE_X108Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.351ns  (logic 0.000ns (0.000%)  route 2.351ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.227ns (routing 0.691ns, distribution 1.536ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[14]
                         net (fo=1, routed)           2.351     2.351    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/src_in
    SLICE_X109Y209       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.227     2.409    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/dest_clk
    SLICE_X109Y209       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[18]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.000ns (0.000%)  route 0.173ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.463ns, distribution 1.091ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[18]
                         net (fo=1, routed)           0.173     0.173    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/src_in
    SLICE_X117Y160       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/dest_clk
    SLICE_X117Y160       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.216ns  (logic 0.000ns (0.000%)  route 0.216ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.545ns (routing 0.463ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[3]
                         net (fo=1, routed)           0.216     0.216    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_over_range/src_in
    SLICE_X108Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.545     1.692    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_over_range/dest_clk
    SLICE_X108Y157       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[19]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.221ns  (logic 0.000ns (0.000%)  route 0.221ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[19]
                         net (fo=1, routed)           0.221     0.221    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/src_in
    SLICE_X118Y148       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/dest_clk
    SLICE_X118Y148       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.223ns  (logic 0.000ns (0.000%)  route 0.223ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.551ns (routing 0.463ns, distribution 1.088ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[14]
                         net (fo=1, routed)           0.223     0.223    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_data_irq/src_in
    SLICE_X109Y143       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.551     1.698    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_data_irq/dest_clk
    SLICE_X109Y143       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.224ns  (logic 0.000ns (0.000%)  route 0.224ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[2]
                         net (fo=1, routed)           0.224     0.224    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_vol/src_in
    SLICE_X113Y158       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_vol/dest_clk
    SLICE_X113Y158       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.226ns  (logic 0.000ns (0.000%)  route 0.226ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.463ns, distribution 1.091ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[14]
                         net (fo=1, routed)           0.226     0.226    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_data_irq/src_in
    SLICE_X110Y160       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_data_irq/dest_clk
    SLICE_X110Y160       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[18]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.237ns  (logic 0.000ns (0.000%)  route 0.237ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.561ns (routing 0.463ns, distribution 1.098ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[18]
                         net (fo=1, routed)           0.237     0.237    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_over_vol/src_in
    SLICE_X115Y147       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.561     1.708    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_over_vol/dest_clk
    SLICE_X115Y147       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.242ns  (logic 0.000ns (0.000%)  route 0.242ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.561ns (routing 0.463ns, distribution 1.098ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.242     0.242    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/src_in
    SLICE_X111Y162       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.561     1.708    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/dest_clk
    SLICE_X111Y162       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.254ns  (logic 0.000ns (0.000%)  route 0.254ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[15]
                         net (fo=1, routed)           0.254     0.254    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/src_in
    SLICE_X110Y162       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/dest_clk
    SLICE_X110Y162       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.255ns  (logic 0.000ns (0.000%)  route 0.255ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.463ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[0]
                         net (fo=1, routed)           0.255     0.255    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/src_in
    SLICE_X117Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/dest_clk
    SLICE_X117Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.551ns  (logic 0.880ns (24.782%)  route 2.671ns (75.218%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.873     2.393    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X107Y170       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.091     2.484 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12/O
                         net (fo=1, routed)           0.260     2.744    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12_n_0
    SLICE_X107Y174       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.123     2.867 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.488     3.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     3.501 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     3.551    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.137ns  (logic 0.794ns (25.311%)  route 2.343ns (74.689%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.750     2.237    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X106Y171       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     2.273 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                         net (fo=1, routed)           0.114     2.387    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    SLICE_X106Y174       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.149     2.536 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.430     2.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.122     3.088 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.989ns  (logic 0.825ns (27.601%)  route 2.164ns (72.399%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.777     2.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X107Y170       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     2.418 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.138     2.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X107Y174       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     2.595 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.177     2.772    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.145     2.917 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.769ns  (logic 0.617ns (22.282%)  route 2.152ns (77.718%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.560     2.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X108Y170       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.089     2.103 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.321     2.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X109Y176       LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.037     2.461 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.205     2.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     2.703 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     2.769    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.765ns  (logic 0.683ns (24.702%)  route 2.082ns (75.298%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.512     1.986    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X108Y170       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     2.021 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.207     2.228    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X109Y176       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.123     2.351 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.291     2.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.051     2.693 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     2.765    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.754ns  (logic 0.687ns (24.946%)  route 2.067ns (75.054%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.546     1.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X108Y170       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     2.049 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_17/O
                         net (fo=1, routed)           0.155     2.204    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_17_n_0
    SLICE_X108Y174       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.148     2.352 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.317     2.669    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     2.705 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.754    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.727ns  (logic 0.700ns (25.669%)  route 2.027ns (74.331%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.680     2.124    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X106Y171       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     2.159 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11/O
                         net (fo=1, routed)           0.142     2.301    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11_n_0
    SLICE_X106Y174       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     2.400 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.156     2.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     2.678 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     2.727    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.604ns  (logic 0.633ns (24.309%)  route 1.971ns (75.691%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.571     1.996    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X108Y170       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.122     2.118 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19/O
                         net (fo=1, routed)           0.150     2.268    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19_n_0
    SLICE_X108Y175       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     2.318 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.201     2.519    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     2.555 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.291ns  (logic 0.297ns (23.005%)  route 0.994ns (76.995%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.793     1.004    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X108Y170       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.054 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19/O
                         net (fo=1, routed)           0.080     1.134    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19_n_0
    SLICE_X108Y175       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.022     1.156 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.105     1.261    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     1.275 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.340ns  (logic 0.315ns (23.507%)  route 1.025ns (76.493%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.851     1.061    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X106Y171       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     1.075 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11/O
                         net (fo=1, routed)           0.074     1.149    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11_n_0
    SLICE_X106Y174       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.041     1.190 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.084     1.274    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     1.324 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.340    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.348ns  (logic 0.306ns (22.700%)  route 1.042ns (77.300%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.761     0.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X108Y170       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     0.995 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.112     1.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X109Y176       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.050     1.157 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.143     1.300    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.022     1.322 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.348    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.354ns  (logic 0.313ns (23.117%)  route 1.041ns (76.883%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.776     0.980    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X108Y170       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     1.016 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_17/O
                         net (fo=1, routed)           0.085     1.101    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_17_n_0
    SLICE_X108Y174       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.059     1.160 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.164     1.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     1.338 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     1.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.358ns  (logic 0.284ns (20.913%)  route 1.074ns (79.087%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.780     1.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X108Y170       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     1.036 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.163     1.199    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X109Y176       LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.014     1.213 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.107     1.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.334 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.358    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.436ns  (logic 0.364ns (25.348%)  route 1.072ns (74.652%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.882     1.132    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X107Y170       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.040     1.172 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.076     1.248    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X107Y174       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.015     1.263 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.088     1.351    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.059     1.410 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.436    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.541ns  (logic 0.363ns (23.556%)  route 1.178ns (76.444%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.881     1.119    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X106Y171       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     1.134 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                         net (fo=1, routed)           0.059     1.193    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    SLICE_X106Y174       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.060     1.253 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.222     1.475    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     1.525 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.541    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.693ns  (logic 0.376ns (22.209%)  route 1.317ns (77.791%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.918     1.150    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X107Y170       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.035     1.185 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12/O
                         net (fo=1, routed)           0.130     1.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12_n_0
    SLICE_X107Y174       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.050     1.365 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.252     1.617    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.059     1.676 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.693    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.385ns  (logic 0.882ns (26.056%)  route 2.503ns (73.944%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.269     1.789    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][15]
    SLICE_X107Y165       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.123     1.912 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.347     2.259    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X104Y166       LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     2.358 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16/O
                         net (fo=1, routed)           0.562     2.920    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16_n_0
    SLICE_X108Y165       LUT5 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.090     3.010 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.275     3.285    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     3.335 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     3.385    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.268ns  (logic 0.909ns (27.815%)  route 2.359ns (72.185%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.311     1.798    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][13]
    SLICE_X106Y166       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     1.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_61/O
                         net (fo=1, routed)           0.240     2.188    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_61_n_0
    SLICE_X105Y165       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     2.312 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_25/O
                         net (fo=1, routed)           0.604     2.916    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_25_n_0
    SLICE_X108Y176       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.049     2.965 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.155     3.120    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.099     3.219 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.268    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.808ns  (logic 0.830ns (29.558%)  route 1.978ns (70.442%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.084     1.528    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][12]
    SLICE_X109Y164       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     1.676 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.527     2.203    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X106Y168       LUT5 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     2.352 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.318     2.670    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     2.759 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     2.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.801ns  (logic 0.800ns (28.561%)  route 2.001ns (71.439%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.172     1.626    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][9]
    SLICE_X107Y164       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.098     1.724 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.119     1.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X107Y166       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.150     1.993 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.644     2.637    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     2.735 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     2.801    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.625ns  (logic 0.816ns (31.086%)  route 1.809ns (68.914%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.041     1.584    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][14]
    SLICE_X108Y164       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.634 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.421     2.055    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X107Y165       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.101     2.156 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.275     2.431    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.122     2.553 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.625    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.623ns  (logic 0.858ns (32.711%)  route 1.765ns (67.289%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.220     1.645    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][10]
    SLICE_X109Y165       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     1.734 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_55/O
                         net (fo=1, routed)           0.095     1.829    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_55_n_0
    SLICE_X108Y165       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099     1.928 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.095     2.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X109Y165       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.123     2.146 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.306     2.452    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.122     2.574 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.623    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.533ns  (logic 0.851ns (33.597%)  route 1.682ns (66.403%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.006     1.480    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][11]
    SLICE_X109Y165       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.100     1.580 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_45/O
                         net (fo=1, routed)           0.207     1.787    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_45_n_0
    SLICE_X109Y165       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     1.939 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.042     1.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X109Y165       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     2.018 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.355     2.373    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.088     2.461 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     2.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.161ns  (logic 0.642ns (29.708%)  route 1.519ns (70.292%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.994     1.407    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][8]
    SLICE_X109Y166       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     1.496 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_25/O
                         net (fo=1, routed)           0.139     1.635    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_25_n_0
    SLICE_X109Y166       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     1.686 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.337     2.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089     2.112 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.053ns  (logic 0.296ns (28.110%)  route 0.757ns (71.890%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.487     0.691    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][8]
    SLICE_X109Y166       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     0.726 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_25/O
                         net (fo=1, routed)           0.075     0.801    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_25_n_0
    SLICE_X109Y166       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     0.823 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.179     1.002    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.035     1.037 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     1.053    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.180ns  (logic 0.370ns (31.356%)  route 0.810ns (68.644%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.493     0.713    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][11]
    SLICE_X109Y165       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.040     0.753 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_45/O
                         net (fo=1, routed)           0.086     0.839    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_45_n_0
    SLICE_X109Y165       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.061     0.900 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.024     0.924    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X109Y165       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.014     0.938 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.181     1.119    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.035     1.154 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.253ns  (logic 0.387ns (30.886%)  route 0.866ns (69.114%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.586     0.797    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][10]
    SLICE_X109Y165       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     0.832 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_55/O
                         net (fo=1, routed)           0.050     0.882    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_55_n_0
    SLICE_X108Y165       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.041     0.923 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.052     0.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X109Y165       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.050     1.025 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.162     1.187    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     1.237 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.253    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.257ns  (logic 0.363ns (28.878%)  route 0.894ns (71.122%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.507     0.757    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][14]
    SLICE_X108Y164       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     0.779 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.216     0.995    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X107Y165       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.041     1.036 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.145     1.181    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.050     1.231 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.257    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.329ns  (logic 0.364ns (27.389%)  route 0.965ns (72.611%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.534     0.744    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][12]
    SLICE_X109Y164       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     0.803 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.255     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X106Y168       LUT5 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.060     1.118 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.160     1.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.313 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.329    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.338ns  (logic 0.361ns (26.981%)  route 0.977ns (73.019%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.578     0.799    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][9]
    SLICE_X107Y164       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     0.839 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.061     0.900    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X107Y166       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.060     0.960 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.314     1.274    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     1.314 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.338    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.585ns  (logic 0.380ns (23.975%)  route 1.205ns (76.025%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.627     0.859    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][15]
    SLICE_X107Y165       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.050     0.909 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.149     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X104Y166       LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.041     1.099 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16/O
                         net (fo=1, routed)           0.268     1.367    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16_n_0
    SLICE_X108Y165       LUT5 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.035     1.402 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.144     1.546    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.022     1.568 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.585    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.597ns  (logic 0.411ns (25.736%)  route 1.186ns (74.264%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.655     0.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][13]
    SLICE_X106Y166       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.060     0.953 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_61/O
                         net (fo=1, routed)           0.123     1.076    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_61_n_0
    SLICE_X105Y165       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.050     1.126 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_25/O
                         net (fo=1, routed)           0.314     1.440    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_25_n_0
    SLICE_X108Y176       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.022     1.462 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.078     1.540    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.041     1.581 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.597    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay           144 Endpoints
Min Delay           144 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.323ns  (logic 0.761ns (32.759%)  route 1.562ns (67.241%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        -0.786ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.392ns
    Source Clock Delay      (SCD):    3.178ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.652ns (routing 1.062ns, distribution 1.590ns)
  Clock Net Delay (Destination): 2.210ns (routing 0.691ns, distribution 1.519ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.652     3.178    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m2_axis_aclk
    RFADC_X0Y2           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.338     3.516 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.580     4.096    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[5]
    SLICE_X109Y156       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.184 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_32/O
                         net (fo=1, routed)           0.136     4.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_32_n_0
    SLICE_X109Y159       LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.091     4.411 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/O
                         net (fo=1, routed)           0.201     4.612    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14_n_0
    SLICE_X108Y164       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098     4.710 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.596     5.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X106Y183       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.146     5.452 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.049     5.501    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X106Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.210     2.392    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.171ns  (logic 0.076ns (6.490%)  route 1.095ns (93.510%))
  Logic Levels:           0  
  Clock Path Skew:        -0.545ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    2.977ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.451ns (routing 1.062ns, distribution 1.389ns)
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.451     2.977    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X83Y151        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y151        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.053 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.095     4.148    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X110Y151       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X110Y151       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.392ns  (logic 0.076ns (19.373%)  route 0.316ns (80.627%))
  Logic Levels:           0  
  Clock Path Skew:        -0.743ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.079ns
    Source Clock Delay      (SCD):    2.822ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.296ns (routing 1.062ns, distribution 1.234ns)
  Clock Net Delay (Destination): 1.897ns (routing 0.691ns, distribution 1.206ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.296     2.822    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X48Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y219        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.898 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.316     3.214    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X46Y221        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.897     2.079    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X46Y221        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.357ns  (logic 0.076ns (21.271%)  route 0.281ns (78.729%))
  Logic Levels:           0  
  Clock Path Skew:        -0.688ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.086ns
    Source Clock Delay      (SCD):    2.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.248ns (routing 1.062ns, distribution 1.186ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.691ns, distribution 1.213ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.248     2.774    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X56Y167        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y167        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.850 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.281     3.131    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X54Y168        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.904     2.086    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X54Y168        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.792ns  (logic 0.863ns (30.910%)  route 1.929ns (69.090%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.617     1.071    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[9]
    SLICE_X109Y160       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     1.169 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_50/O
                         net (fo=1, routed)           0.345     1.514    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_50_n_0
    SLICE_X106Y160       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.123     1.637 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16/O
                         net (fo=1, routed)           0.257     1.894    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16_n_0
    SLICE_X107Y166       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     1.984 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.644     2.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     2.726 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     2.792    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.739ns  (logic 0.816ns (29.792%)  route 1.923ns (70.208%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.072     1.516    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[12]
    SLICE_X109Y161       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.052     1.568 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_33/O
                         net (fo=1, routed)           0.146     1.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_33_n_0
    SLICE_X108Y162       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     1.837 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.093     1.930    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X108Y164       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.051     1.981 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.563     2.544    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     2.690 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     2.739    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.390ns  (logic 0.810ns (33.891%)  route 1.580ns (66.109%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.751     1.238    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[13]
    SLICE_X107Y158       LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     1.386 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56/O
                         net (fo=1, routed)           0.090     1.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56_n_0
    SLICE_X107Y158       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     1.564 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20/O
                         net (fo=1, routed)           0.198     1.762    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20_n_0
    SLICE_X107Y162       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     1.799 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.492     2.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     2.341 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.390    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.282ns  (logic 0.961ns (42.112%)  route 1.321ns (57.888%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.681     1.155    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[11]
    SLICE_X109Y160       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     1.303 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_43/O
                         net (fo=1, routed)           0.098     1.401    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_43_n_0
    SLICE_X109Y162       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     1.502 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.115     1.617    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X109Y165       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.150     1.767 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.355     2.122    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.088     2.210 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     2.282    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.265ns  (logic 0.720ns (31.788%)  route 1.545ns (68.212%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.564     1.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[14]
    SLICE_X109Y158       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     1.146 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43/O
                         net (fo=1, routed)           0.200     1.346    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43_n_0
    SLICE_X108Y163       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.382 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_15/O
                         net (fo=1, routed)           0.299     1.681    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_15_n_0
    SLICE_X108Y177       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.051     1.732 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4/O
                         net (fo=1, routed)           0.410     2.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.051     2.193 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.081ns  (logic 0.720ns (34.599%)  route 1.361ns (65.401%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.679     1.092    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[8]
    SLICE_X109Y160       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.091     1.183 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_41/O
                         net (fo=1, routed)           0.091     1.274    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_41_n_0
    SLICE_X109Y160       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     1.364 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.205     1.569    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X109Y166       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     1.606 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.337     1.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089     2.032 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.967ns  (logic 0.323ns (33.402%)  route 0.644ns (66.598%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.299     0.503    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[8]
    SLICE_X109Y160       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.035     0.538 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_41/O
                         net (fo=1, routed)           0.047     0.585    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_41_n_0
    SLICE_X109Y160       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.620 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.103     0.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X109Y166       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     0.737 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.179     0.916    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.035     0.951 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     0.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.971ns  (logic 0.343ns (35.324%)  route 0.628ns (64.676%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.315     0.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[15]
    SLICE_X108Y158       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.035     0.582 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57/O
                         net (fo=1, routed)           0.082     0.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57_n_0
    SLICE_X108Y163       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.040     0.704 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_17/O
                         net (fo=1, routed)           0.070     0.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_17_n_0
    SLICE_X108Y165       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.014     0.788 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.144     0.932    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.022     0.954 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     0.971    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.972ns  (logic 0.353ns (36.317%)  route 0.619ns (63.683%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.250     0.461    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[10]
    SLICE_X109Y157       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.035     0.496 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_52/O
                         net (fo=1, routed)           0.120     0.616    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_52_n_0
    SLICE_X109Y162       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.035     0.651 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.071     0.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X109Y165       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.022     0.744 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.162     0.906    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     0.956 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     0.972    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.045ns  (logic 0.415ns (39.713%)  route 0.630ns (60.287%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.313     0.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[11]
    SLICE_X109Y160       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.059     0.592 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_43/O
                         net (fo=1, routed)           0.051     0.643    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_43_n_0
    SLICE_X109Y162       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     0.684 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.059     0.743    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X109Y165       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.060     0.803 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.181     0.984    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.035     1.019 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.088ns  (logic 0.325ns (29.871%)  route 0.763ns (70.129%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.269     0.519    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[14]
    SLICE_X109Y158       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.015     0.534 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43/O
                         net (fo=1, routed)           0.104     0.638    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43_n_0
    SLICE_X108Y163       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.653 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_15/O
                         net (fo=1, routed)           0.153     0.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_15_n_0
    SLICE_X108Y177       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023     0.829 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4/O
                         net (fo=1, routed)           0.211     1.040    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.022     1.062 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.149ns  (logic 0.368ns (32.028%)  route 0.781ns (67.972%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.361     0.599    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[13]
    SLICE_X107Y158       LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.059     0.658 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56/O
                         net (fo=1, routed)           0.042     0.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56_n_0
    SLICE_X107Y158       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     0.735 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20/O
                         net (fo=1, routed)           0.101     0.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20_n_0
    SLICE_X107Y162       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     0.850 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.261     1.111    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     1.133 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.149    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.293ns  (logic 0.364ns (28.152%)  route 0.929ns (71.848%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.515     0.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[12]
    SLICE_X109Y161       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.022     0.747 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_33/O
                         net (fo=1, routed)           0.077     0.824    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_33_n_0
    SLICE_X108Y162       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.050     0.874 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.049     0.923    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X108Y164       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.023     0.946 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.272     1.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.059     1.277 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.293    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.310ns  (logic 0.386ns (29.466%)  route 0.924ns (70.534%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.289     0.510    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[9]
    SLICE_X109Y160       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     0.550 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_50/O
                         net (fo=1, routed)           0.164     0.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_50_n_0
    SLICE_X106Y160       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.050     0.764 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16/O
                         net (fo=1, routed)           0.133     0.897    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16_n_0
    SLICE_X107Y166       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.035     0.932 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.314     1.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     1.286 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.310    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.156ns  (logic 0.038ns (24.344%)  route 0.118ns (75.656%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.468ns
    Source Clock Delay      (SCD):    1.496ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.234ns (routing 0.578ns, distribution 0.656ns)
  Clock Net Delay (Destination): 1.321ns (routing 0.463ns, distribution 0.858ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.234     1.496    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X56Y167        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y167        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.534 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.118     1.652    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X54Y168        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.321     1.468    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X54Y168        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.038ns (20.754%)  route 0.145ns (79.245%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.460ns
    Source Clock Delay      (SCD):    1.517ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.255ns (routing 0.578ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.313ns (routing 0.463ns, distribution 0.850ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.255     1.517    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X48Y219        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y219        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.555 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.145     1.700    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X46Y221        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.313     1.460    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X46Y221        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.810ns  (logic 0.921ns (32.776%)  route 1.889ns (67.224%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.945     1.432    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[13]
    SLICE_X107Y179       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.149     1.581 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_50/O
                         net (fo=1, routed)           0.378     1.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_50_n_0
    SLICE_X105Y179       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.146     2.105 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.428     2.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X108Y177       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.583 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.089     2.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.089     2.761 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.810    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.607ns  (logic 0.893ns (34.254%)  route 1.714ns (65.746%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.962     1.482    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[15]
    SLICE_X107Y178       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     1.570 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_60/O
                         net (fo=1, routed)           0.040     1.610    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_60_n_0
    SLICE_X107Y178       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.037     1.647 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_18/O
                         net (fo=1, routed)           0.563     2.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_18_n_0
    SLICE_X109Y177       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125     2.335 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.099     2.434    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.123     2.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     2.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.205ns  (logic 0.755ns (34.240%)  route 1.450ns (65.760%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.784     1.327    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[14]
    SLICE_X108Y178       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.362 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_45/O
                         net (fo=1, routed)           0.041     1.403    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_45_n_0
    SLICE_X108Y178       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     1.439 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.143     1.582    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X108Y177       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     1.672 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4/O
                         net (fo=1, routed)           0.410     2.082    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.051     2.133 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.941ns  (logic 0.629ns (32.406%)  route 1.312ns (67.594%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.711     1.155    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[12]
    SLICE_X111Y179       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.191 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.469     1.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X106Y179       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     1.759 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.083     1.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     1.892 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     1.941    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.818ns  (logic 0.717ns (39.439%)  route 1.101ns (60.561%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.842     1.296    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[9]
    SLICE_X110Y181       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.123     1.419 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24/O
                         net (fo=1, routed)           0.039     1.458    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24_n_0
    SLICE_X110Y181       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     1.547 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.154     1.701    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     1.752 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     1.818    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.798ns  (logic 0.776ns (43.159%)  route 1.022ns (56.841%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.703     1.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[11]
    SLICE_X109Y181       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.090     1.267 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15/O
                         net (fo=1, routed)           0.145     1.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15_n_0
    SLICE_X109Y180       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     1.502 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.102     1.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.122     1.726 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     1.798    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.699ns  (logic 0.760ns (44.732%)  route 0.939ns (55.268%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.711     1.136    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[10]
    SLICE_X108Y179       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.146     1.282 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.041     1.323    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X108Y179       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     1.413 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.138     1.551    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     1.650 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     1.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.578ns  (logic 0.590ns (37.389%)  route 0.988ns (62.611%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.649     1.062    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[8]
    SLICE_X110Y181       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.101 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.041     1.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X110Y181       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     1.230 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.249     1.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.529 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     1.578    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.756ns  (logic 0.276ns (36.508%)  route 0.480ns (63.492%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.313     0.517    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[8]
    SLICE_X110Y181       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.532 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.024     0.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X110Y181       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.035     0.591 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.127     0.718    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     0.740 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     0.756    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.805ns  (logic 0.347ns (43.106%)  route 0.458ns (56.894%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.346     0.557    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[10]
    SLICE_X108Y179       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.059     0.616 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.022     0.638    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X108Y179       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     0.674 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.074     0.748    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     0.789 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     0.805    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.807ns  (logic 0.340ns (42.131%)  route 0.467ns (57.869%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.316     0.536    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[11]
    SLICE_X109Y181       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.035     0.571 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15/O
                         net (fo=1, routed)           0.072     0.643    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15_n_0
    SLICE_X109Y180       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.035     0.678 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.053     0.731    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.050     0.781 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     0.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.866ns  (logic 0.328ns (37.875%)  route 0.538ns (62.125%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.410     0.631    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[9]
    SLICE_X110Y181       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.050     0.681 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24/O
                         net (fo=1, routed)           0.022     0.703    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24_n_0
    SLICE_X110Y181       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     0.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.082     0.820    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     0.842 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     0.866    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.914ns  (logic 0.288ns (31.510%)  route 0.626ns (68.490%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.345     0.555    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[12]
    SLICE_X111Y179       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.570 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.225     0.795    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X106Y179       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.041     0.836 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.040     0.876    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.022     0.898 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     0.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.045ns  (logic 0.336ns (32.153%)  route 0.709ns (67.847%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.378     0.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[14]
    SLICE_X108Y178       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     0.642 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_45/O
                         net (fo=1, routed)           0.022     0.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_45_n_0
    SLICE_X108Y178       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     0.678 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.072     0.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X108Y177       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     0.786 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4/O
                         net (fo=1, routed)           0.211     0.997    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.022     1.019 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.211ns  (logic 0.382ns (31.544%)  route 0.829ns (68.456%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.470     0.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[15]
    SLICE_X107Y178       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     0.737 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_60/O
                         net (fo=1, routed)           0.022     0.759    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_60_n_0
    SLICE_X107Y178       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.014     0.773 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_18/O
                         net (fo=1, routed)           0.267     1.040    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_18_n_0
    SLICE_X109Y177       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.051     1.091 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.053     1.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     1.194 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.211    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.352ns  (logic 0.414ns (30.621%)  route 0.938ns (69.379%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.462     0.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[13]
    SLICE_X107Y179       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.060     0.760 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_50/O
                         net (fo=1, routed)           0.190     0.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_50_n_0
    SLICE_X105Y179       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.059     1.009 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.227     1.236    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X108Y177       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.258 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.043     1.301    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.035     1.336 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.352    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.476ns  (logic 1.291ns (37.140%)  route 2.185ns (62.860%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.143     1.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[15]
    SLICE_X112Y186       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.100     2.059 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_64/O
                         net (fo=1, routed)           0.091     2.150    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_64_n_0
    SLICE_X111Y186       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.090     2.240 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.289     2.529    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X109Y184       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     2.619 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.279     2.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     2.997 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.333     3.330    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.426 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     3.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.426ns  (logic 1.235ns (36.048%)  route 2.191ns (63.952%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.094     1.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[14]
    SLICE_X112Y186       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     2.077 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_59/O
                         net (fo=1, routed)           0.095     2.172    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_59_n_0
    SLICE_X111Y186       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     2.207 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.193     2.400    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X109Y185       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     2.490 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.449     2.939    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     3.029 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.288     3.317    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.354 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     3.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.355ns  (logic 1.400ns (41.729%)  route 1.955ns (58.271%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.188     2.108    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[13]
    SLICE_X110Y186       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.090     2.198 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40/O
                         net (fo=1, routed)           0.281     2.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40_n_0
    SLICE_X109Y182       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     2.624 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                         net (fo=1, routed)           0.200     2.824    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.923 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.237     3.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     3.306 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.073ns  (logic 1.200ns (39.050%)  route 1.873ns (60.950%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.076     1.929    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[12]
    SLICE_X110Y186       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.125     2.054 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.254     2.308    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X108Y183       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.123     2.431 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.494     2.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     3.024 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     3.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.961ns  (logic 1.149ns (38.804%)  route 1.812ns (61.196%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.333     2.174    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[8]
    SLICE_X105Y183       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.089     2.263 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                         net (fo=1, routed)           0.044     2.307    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    SLICE_X105Y183       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.097     2.404 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.386     2.790    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     2.912 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.961    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.579ns  (logic 1.072ns (41.566%)  route 1.507ns (58.433%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.112     1.906    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[9]
    SLICE_X112Y185       LUT5 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.100     2.006 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.243     2.249    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X109Y184       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7/O
                         net (fo=1, routed)           0.086     2.425    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.088     2.513 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     2.579    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.345ns  (logic 1.117ns (47.633%)  route 1.228ns (52.367%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.068     1.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[11]
    SLICE_X109Y182       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.123     2.048 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.048     2.096    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X109Y182       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.100     2.196 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                         net (fo=1, routed)           0.040     2.236    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.037     2.273 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     2.345    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.193ns  (logic 0.954ns (43.502%)  route 1.239ns (56.498%))
  Logic Levels:           3  (LUT3=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.067     1.846    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[10]
    SLICE_X108Y182       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     1.882 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_8/O
                         net (fo=1, routed)           0.037     1.919    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_8_n_0
    SLICE_X108Y182       LUT3 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     2.008 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.086     2.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     2.144 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.193    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.059ns  (logic 0.454ns (42.871%)  route 0.605ns (57.129%))
  Logic Levels:           3  (LUT3=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.527     0.909    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[10]
    SLICE_X108Y182       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.015     0.924 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_8/O
                         net (fo=1, routed)           0.021     0.945    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_8_n_0
    SLICE_X108Y182       LUT3 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     0.980 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.041     1.021    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.022     1.043 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.124ns  (logic 0.521ns (46.352%)  route 0.603ns (53.648%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.527     0.944    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[11]
    SLICE_X109Y182       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.050     0.994 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.026     1.020    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X109Y182       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.040     1.060 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                         net (fo=1, routed)           0.024     1.084    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.014     1.098 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.124    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.255ns  (logic 0.509ns (40.558%)  route 0.746ns (59.442%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.550     0.949    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[9]
    SLICE_X112Y185       LUT5 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.040     0.989 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.124     1.113    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X109Y184       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.035     1.148 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7/O
                         net (fo=1, routed)           0.048     1.196    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.035     1.231 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.441ns  (logic 0.528ns (36.641%)  route 0.913ns (63.359%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.670     1.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[8]
    SLICE_X105Y183       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     1.108 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                         net (fo=1, routed)           0.025     1.133    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    SLICE_X105Y183       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.040     1.173 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.202     1.375    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     1.425 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     1.441    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.474ns  (logic 0.560ns (37.992%)  route 0.914ns (62.008%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.529     0.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[12]
    SLICE_X110Y186       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.051     0.998 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.133     1.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X108Y183       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     1.181 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.236     1.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.458 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.474    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.606ns  (logic 0.623ns (38.792%)  route 0.983ns (61.208%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.596     1.025    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[13]
    SLICE_X110Y186       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.035     1.060 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40/O
                         net (fo=1, routed)           0.143     1.203    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40_n_0
    SLICE_X109Y182       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     1.262 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                         net (fo=1, routed)           0.106     1.368    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.409 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.122     1.531    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     1.590 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.606    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.655ns  (logic 0.576ns (34.804%)  route 1.079ns (65.196%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.545     0.962    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[14]
    SLICE_X112Y186       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.061     1.023 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_59/O
                         net (fo=1, routed)           0.050     1.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_59_n_0
    SLICE_X111Y186       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.014     1.087 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.101     1.188    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X109Y185       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.035     1.223 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.211     1.434    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.035     1.469 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.146     1.615    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.629 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.681ns  (logic 0.602ns (35.812%)  route 1.079ns (64.188%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.566     0.977    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_25_0[15]
    SLICE_X112Y186       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.040     1.017 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_64/O
                         net (fo=1, routed)           0.050     1.067    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_64_n_0
    SLICE_X111Y186       LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.035     1.102 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.133     1.235    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X109Y184       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.035     1.270 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.140     1.410    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.041     1.451 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.173     1.624    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.664 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.681    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.220ns  (logic 1.225ns (29.028%)  route 2.995ns (70.972%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.524     2.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[14]
    SLICE_X110Y196       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     2.408 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_89/O
                         net (fo=1, routed)           0.329     2.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_89_n_0
    SLICE_X110Y196       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.125     2.862 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_64/O
                         net (fo=1, routed)           0.084     2.946    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_64_n_0
    SLICE_X110Y195       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.037     2.983 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28/O
                         net (fo=1, routed)           0.148     3.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28_n_0
    SLICE_X111Y191       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.089     3.220 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.550     3.770    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     3.823 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.288     4.111    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     4.148 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     4.220    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.610ns  (logic 1.088ns (30.139%)  route 2.522ns (69.861%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.489     2.342    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[12]
    SLICE_X109Y196       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     2.381 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_58/O
                         net (fo=1, routed)           0.092     2.473    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_58_n_0
    SLICE_X108Y196       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     2.509 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28/O
                         net (fo=1, routed)           0.470     2.979    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28_n_0
    SLICE_X106Y192       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     3.103 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.422     3.525    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.036     3.561 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     3.610    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.573ns  (logic 1.356ns (37.951%)  route 2.217ns (62.049%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.457     2.273    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[15]
    SLICE_X110Y195       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.145     2.418 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_69/O
                         net (fo=1, routed)           0.045     2.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_69_n_0
    SLICE_X110Y195       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.101     2.564 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_29/O
                         net (fo=1, routed)           0.040     2.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_29_n_0
    SLICE_X110Y195       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     2.656 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_7/O
                         net (fo=1, routed)           0.292     2.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_7_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.146     3.094 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.333     3.427    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.523 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     3.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.444ns  (logic 1.328ns (38.560%)  route 2.116ns (61.440%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.441     2.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[13]
    SLICE_X109Y196       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.123     2.484 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_28/O
                         net (fo=1, routed)           0.093     2.577    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_28_n_0
    SLICE_X108Y196       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.627 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.296     2.923    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     3.012 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.237     3.249    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     3.395 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.444    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.368ns  (logic 1.113ns (33.046%)  route 2.255ns (66.954%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.487     2.281    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[9]
    SLICE_X112Y195       LUT4 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     2.318 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46/O
                         net (fo=1, routed)           0.235     2.553    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46_n_0
    SLICE_X110Y196       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.100     2.653 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.245     2.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X109Y191       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.037     2.935 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.222     3.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.302 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     3.368    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.257ns  (logic 1.185ns (36.383%)  route 2.072ns (63.617%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.535     2.392    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[11]
    SLICE_X111Y195       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.146     2.538 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.140     2.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X110Y195       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.037     2.715 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.325     3.040    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.145     3.185 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     3.257    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.209ns  (logic 1.162ns (36.211%)  route 2.047ns (63.789%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.556     2.397    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[8]
    SLICE_X112Y195       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.125     2.522 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                         net (fo=1, routed)           0.090     2.612    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    SLICE_X111Y195       LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.050     2.662 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.352     3.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.146     3.160 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     3.209    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.183ns  (logic 0.994ns (31.228%)  route 2.189ns (68.772%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.612     2.391    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[10]
    SLICE_X111Y195       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     2.427 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.233     2.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X111Y195       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.090     2.750 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.295     3.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     3.134 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     3.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.520ns  (logic 0.468ns (30.789%)  route 1.052ns (69.211%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.784     1.166    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[10]
    SLICE_X111Y195       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.015     1.181 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.097     1.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X111Y195       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.036     1.314 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.155     1.469    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.504 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.542ns  (logic 0.535ns (34.695%)  route 1.007ns (65.305%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.775     1.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[8]
    SLICE_X112Y195       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.051     1.229 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                         net (fo=1, routed)           0.048     1.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    SLICE_X111Y195       LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.022     1.299 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.168     1.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.059     1.526 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     1.542    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.579ns  (logic 0.549ns (34.769%)  route 1.030ns (65.231%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.766     1.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[11]
    SLICE_X111Y195       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.059     1.242 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.068     1.310    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X110Y195       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.014     1.324 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.170     1.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.059     1.553 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.579    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.649ns  (logic 0.595ns (36.082%)  route 1.054ns (63.918%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.718     1.147    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[13]
    SLICE_X109Y196       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.050     1.197 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_28/O
                         net (fo=1, routed)           0.049     1.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_28_n_0
    SLICE_X108Y196       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.268 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.149     1.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.035     1.452 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.122     1.574    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     1.633 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.663ns  (logic 0.526ns (31.630%)  route 1.137ns (68.370%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.740     1.139    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[9]
    SLICE_X112Y195       LUT4 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.153 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46/O
                         net (fo=1, routed)           0.122     1.275    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46_n_0
    SLICE_X110Y196       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.040     1.315 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.131     1.446    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X109Y191       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.014     1.460 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.120     1.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     1.639 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.663    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.749ns  (logic 0.632ns (36.135%)  route 1.117ns (63.865%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.729     1.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[15]
    SLICE_X110Y195       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.059     1.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_69/O
                         net (fo=1, routed)           0.025     1.224    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_69_n_0
    SLICE_X110Y195       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.041     1.265 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_29/O
                         net (fo=1, routed)           0.024     1.289    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_29_n_0
    SLICE_X110Y195       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.022     1.311 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_7/O
                         net (fo=1, routed)           0.149     1.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_7_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.059     1.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.173     1.692    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.732 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     1.749    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.774ns  (logic 0.512ns (28.861%)  route 1.262ns (71.139%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.740     1.158    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[12]
    SLICE_X109Y196       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.173 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_58/O
                         net (fo=1, routed)           0.048     1.221    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_58_n_0
    SLICE_X108Y196       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     1.236 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28/O
                         net (fo=1, routed)           0.245     1.481    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28_n_0
    SLICE_X106Y192       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.531 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.213     1.744    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.014     1.758 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.076ns  (logic 0.576ns (27.746%)  route 1.500ns (72.254%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.755     1.172    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[14]
    SLICE_X110Y196       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     1.195 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_89/O
                         net (fo=1, routed)           0.165     1.360    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_89_n_0
    SLICE_X110Y196       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.050     1.410 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_64/O
                         net (fo=1, routed)           0.047     1.457    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_64_n_0
    SLICE_X110Y195       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.014     1.471 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28/O
                         net (fo=1, routed)           0.077     1.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28_n_0
    SLICE_X111Y191       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.035     1.583 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.284     1.867    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     1.890 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.146     2.036    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     2.050 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     2.076    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  clk_pl_0

Max Delay            77 Endpoints
Min Delay            77 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.573ns  (logic 0.177ns (4.954%)  route 3.396ns (95.046%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.660ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.440ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.258ns (routing 0.691ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.367     7.580    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X113Y191       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.070     7.650 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     7.673    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X113Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.258     2.440    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X113Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.562ns  (logic 0.177ns (4.969%)  route 3.385ns (95.031%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.671ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.247ns (routing 0.691ns, distribution 1.556ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.356     7.569    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X110Y201       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.070     7.639 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     7.662    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X110Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X110Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.505ns  (logic 0.219ns (6.248%)  route 3.286ns (93.752%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.735ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.365ns
    Source Clock Delay      (SCD):    4.100ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.389ns (routing 1.864ns, distribution 1.525ns)
  Clock Net Delay (Destination): 2.183ns (routing 0.691ns, distribution 1.492ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.389     4.100    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.179 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.006     6.185    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.213 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       1.263     7.476    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/src_in
    SLICE_X105Y198       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.112     7.588 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.017     7.605    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X105Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.183     2.365    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/dest_clk
    SLICE_X105Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.989ns  (logic 1.342ns (26.899%)  route 3.647ns (73.101%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.328     3.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[15]
    SLICE_X106Y187       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     3.290 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_97/O
                         net (fo=1, routed)           0.038     3.328    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_97_n_0
    SLICE_X106Y187       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     3.363 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_80/O
                         net (fo=1, routed)           0.146     3.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_80_n_0
    SLICE_X105Y187       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.149     3.658 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_39/O
                         net (fo=1, routed)           0.220     3.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_39_n_0
    SLICE_X105Y187       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     3.928 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9/O
                         net (fo=1, routed)           0.532     4.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     4.510 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.333     4.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     4.939 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     4.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.680ns  (logic 1.113ns (23.782%)  route 3.567ns (76.218%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.354     3.185    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[14]
    SLICE_X106Y187       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.097     3.282 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_92/O
                         net (fo=1, routed)           0.183     3.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_92_n_0
    SLICE_X105Y187       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     3.500 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66/O
                         net (fo=1, routed)           0.130     3.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66_n_0
    SLICE_X104Y188       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     3.669 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30/O
                         net (fo=1, routed)           0.217     3.886    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30_n_0
    SLICE_X105Y188       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     3.921 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.323     4.244    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     4.283 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.288     4.571    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     4.608 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     4.680    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.294ns  (logic 1.349ns (31.416%)  route 2.945ns (68.584%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.171     3.091    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[13]
    SLICE_X106Y189       LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.124     3.215 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.049     3.264    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X106Y189       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.123     3.387 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.439     3.826    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     3.862 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.237     4.099    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     4.245 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     4.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.286ns  (logic 1.014ns (23.658%)  route 3.272ns (76.342%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           2.579     3.358    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[10]
    SLICE_X106Y190       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.036     3.394 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.095     3.489    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X107Y190       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     3.542 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.549     4.091    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     4.237 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     4.286    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.128ns  (logic 1.211ns (29.336%)  route 2.917ns (70.664%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           2.150     2.991    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[8]
    SLICE_X106Y190       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.123     3.114 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11/O
                         net (fo=1, routed)           0.159     3.273    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11_n_0
    SLICE_X107Y190       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     3.421 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.559     3.980    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     4.079 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     4.128    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.963ns  (logic 1.189ns (30.003%)  route 2.774ns (69.997%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.187     3.040    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[12]
    SLICE_X106Y189       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.150     3.190 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_24/O
                         net (fo=1, routed)           0.116     3.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_24_n_0
    SLICE_X106Y192       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     3.456 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.422     3.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.036     3.914 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     3.963    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.856ns  (logic 1.118ns (28.994%)  route 2.738ns (71.006%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.117     2.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[11]
    SLICE_X107Y191       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     3.013 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14/O
                         net (fo=1, routed)           0.328     3.341    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14_n_0
    SLICE_X109Y191       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.123     3.464 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.221     3.685    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     3.784 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     3.856    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.717ns  (logic 0.533ns (31.043%)  route 1.184ns (68.957%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.964     1.363    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[9]
    SLICE_X108Y191       LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.040     1.403 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/O
                         net (fo=1, routed)           0.076     1.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13_n_0
    SLICE_X109Y191       LUT6 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.035     1.514 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.120     1.634    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     1.693 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.909ns  (logic 0.523ns (27.397%)  route 1.386ns (72.603%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.075     1.492    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[11]
    SLICE_X107Y191       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.507 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14/O
                         net (fo=1, routed)           0.171     1.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14_n_0
    SLICE_X109Y191       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.050     1.728 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.114     1.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.041     1.883 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.909    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.945ns  (logic 0.552ns (28.380%)  route 1.393ns (71.620%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.103     1.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[12]
    SLICE_X106Y189       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.060     1.581 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_24/O
                         net (fo=1, routed)           0.061     1.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_24_n_0
    SLICE_X106Y192       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.060     1.702 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.213     1.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.014     1.929 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     1.945    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.011ns  (logic 0.553ns (27.499%)  route 1.458ns (72.501%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.074     1.477    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[8]
    SLICE_X106Y190       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     1.527 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11/O
                         net (fo=1, routed)           0.081     1.608    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11_n_0
    SLICE_X107Y190       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     1.667 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.287     1.954    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     2.011    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.094ns  (logic 0.602ns (28.749%)  route 1.492ns (71.251%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.100     1.529    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[13]
    SLICE_X106Y189       LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.050     1.579 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.027     1.606    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X106Y189       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.050     1.656 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.227     1.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     1.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.122     2.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     2.078 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     2.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.139ns  (logic 0.478ns (22.347%)  route 1.661ns (77.653%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.313     1.695    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[10]
    SLICE_X106Y190       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     1.709 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.051     1.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X107Y190       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     1.783 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.281     2.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.059     2.123 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     2.139    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.333ns  (logic 0.529ns (22.675%)  route 1.804ns (77.325%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.190     1.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[14]
    SLICE_X106Y187       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.040     1.647 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_92/O
                         net (fo=1, routed)           0.093     1.740    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_92_n_0
    SLICE_X105Y187       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.014     1.754 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66/O
                         net (fo=1, routed)           0.069     1.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66_n_0
    SLICE_X104Y188       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.015     1.838 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30/O
                         net (fo=1, routed)           0.115     1.953    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30_n_0
    SLICE_X105Y188       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.014     1.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.165     2.132    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     2.147 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.146     2.293    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     2.307 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     2.333    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.479ns  (logic 0.628ns (25.333%)  route 1.851ns (74.667%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.181     1.592    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[15]
    SLICE_X106Y187       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.059     1.651 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_97/O
                         net (fo=1, routed)           0.021     1.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_97_n_0
    SLICE_X106Y187       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.014     1.686 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_80/O
                         net (fo=1, routed)           0.076     1.762    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_80_n_0
    SLICE_X105Y187       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.060     1.822 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_39/O
                         net (fo=1, routed)           0.111     1.933    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_39_n_0
    SLICE_X105Y187       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     1.955 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9/O
                         net (fo=1, routed)           0.272     2.227    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.022     2.249 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.173     2.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     2.462 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     2.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.855ns  (logic 0.094ns (5.067%)  route 1.761ns (94.933%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.573ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.644ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 1.497ns (routing 0.463ns, distribution 1.034ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.706     4.027    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/src_in
    SLICE_X105Y198       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.038     4.065 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     4.072    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X105Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.497     1.644    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/dest_clk
    SLICE_X105Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.879ns  (logic 0.077ns (4.098%)  route 1.802ns (95.902%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.528ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.689ns
    Source Clock Delay      (SCD):    2.217ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.850ns (routing 1.007ns, distribution 0.843ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.463ns, distribution 1.079ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.850     2.217    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X80Y118        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y118        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.256 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.048     3.304    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.321 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=36404, routed)       0.747     4.068    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X110Y201       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.021     4.089 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     4.096    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X110Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.542     1.689    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X110Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.917ns  (logic 1.367ns (23.103%)  route 4.550ns (76.897%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        2.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.412ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.230ns (routing 0.691ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.775     3.606    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[14]
    SLICE_X108Y194       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.150     3.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_94/O
                         net (fo=1, routed)           0.376     4.132    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_94_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     4.220 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_72/O
                         net (fo=1, routed)           0.141     4.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_72_n_0
    SLICE_X107Y193       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.099     4.460 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.449     4.909    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X109Y192       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     4.946 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10/O
                         net (fo=1, routed)           0.449     5.395    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.125     5.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.288     5.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     5.845 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     5.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.230     2.412    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.114ns  (logic 1.155ns (22.585%)  route 3.959ns (77.415%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           2.717     3.496    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[10]
    SLICE_X109Y195       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     3.535 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_30/O
                         net (fo=1, routed)           0.096     3.631    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_30_n_0
    SLICE_X109Y193       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     3.721 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.548     4.269    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X107Y190       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     4.370 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.549     4.919    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.065 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     5.114    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.481ns  (logic 1.065ns (23.767%)  route 3.416ns (76.233%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           2.279     3.120    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[8]
    SLICE_X109Y195       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     3.157 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.391     3.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X107Y193       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     3.585 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.138     3.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X107Y190       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051     3.774 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.559     4.333    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     4.432 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     4.481    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.377ns  (logic 1.204ns (27.507%)  route 3.173ns (72.493%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.411     3.227    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[15]
    SLICE_X109Y194       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.123     3.350 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_76/O
                         net (fo=1, routed)           0.090     3.440    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_76_n_0
    SLICE_X108Y194       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.036     3.476 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34/O
                         net (fo=1, routed)           0.086     3.562    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34_n_0
    SLICE_X108Y193       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.097     3.659 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8/O
                         net (fo=1, routed)           0.203     3.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     3.898 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.333     4.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     4.327 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.050     4.377    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.265ns  (logic 1.087ns (25.487%)  route 3.178ns (74.513%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.664     3.517    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[12]
    SLICE_X106Y192       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     3.616 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26/O
                         net (fo=1, routed)           0.043     3.659    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26_n_0
    SLICE_X106Y192       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     3.758 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.422     4.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.036     4.216 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.049     4.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.171ns  (logic 1.170ns (28.051%)  route 3.001ns (71.949%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.381     3.175    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[9]
    SLICE_X109Y195       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.088     3.263 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42/O
                         net (fo=1, routed)           0.173     3.436    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42_n_0
    SLICE_X109Y193       LUT6 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.091     3.527 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14/O
                         net (fo=1, routed)           0.159     3.686    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14_n_0
    SLICE_X109Y191       LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.052     3.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.222     3.960    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     4.105 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.066     4.171    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.136ns  (logic 1.242ns (30.029%)  route 2.894ns (69.971%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.434ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.367     3.287    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[13]
    SLICE_X108Y193       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     3.377 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/O
                         net (fo=1, routed)           0.095     3.472    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34_n_0
    SLICE_X108Y192       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.036     3.508 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.146     3.654    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     3.704 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.237     3.941    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     4.087 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     4.136    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.911ns  (logic 1.107ns (28.305%)  route 2.804ns (71.695%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.691ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.417     3.274    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[11]
    SLICE_X109Y192       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     3.327 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.094     3.421    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X109Y191       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.098     3.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.221     3.740    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     3.839 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.072     3.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.911ns  (logic 0.521ns (27.263%)  route 1.390ns (72.737%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.200     1.617    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[11]
    SLICE_X109Y192       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     1.640 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.050     1.690    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X109Y191       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.040     1.730 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.114     1.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X109Y182       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.041     1.885 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.026     1.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.025ns  (logic 0.559ns (27.605%)  route 1.466ns (72.395%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.199     1.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[13]
    SLICE_X108Y193       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.035     1.663 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/O
                         net (fo=1, routed)           0.050     1.713    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34_n_0
    SLICE_X108Y192       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     1.727 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.079     1.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X108Y187       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     1.828 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.122     1.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     2.009 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     2.025    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.062ns  (logic 0.550ns (26.673%)  route 1.512ns (73.327%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.691ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.691ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.463ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.202     1.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[9]
    SLICE_X109Y195       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.035     1.636 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42/O
                         net (fo=1, routed)           0.086     1.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42_n_0
    SLICE_X109Y193       LUT6 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.035     1.757 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14/O
                         net (fo=1, routed)           0.080     1.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14_n_0
    SLICE_X109Y191       LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.022     1.859 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.120     1.979    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X109Y183       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     2.038 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     2.062    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.544     1.691    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.116ns  (logic 0.514ns (24.291%)  route 1.602ns (75.709%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.350     1.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[12]
    SLICE_X106Y192       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.809 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26/O
                         net (fo=1, routed)           0.023     1.832    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26_n_0
    SLICE_X106Y192       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.041     1.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.213     2.086    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.014     2.100 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.016     2.116    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.178ns  (logic 0.569ns (26.125%)  route 1.609ns (73.875%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.463ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.219     1.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[15]
    SLICE_X109Y194       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.050     1.680 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_76/O
                         net (fo=1, routed)           0.048     1.728    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_76_n_0
    SLICE_X108Y194       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.014     1.742 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34/O
                         net (fo=1, routed)           0.048     1.790    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34_n_0
    SLICE_X108Y193       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.040     1.830 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8/O
                         net (fo=1, routed)           0.104     1.934    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8_n_0
    SLICE_X108Y190       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     1.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.173     2.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X108Y177       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     2.161 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.017     2.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.548     1.695    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.217ns  (logic 0.494ns (22.282%)  route 1.723ns (77.718%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.154     1.557    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[8]
    SLICE_X109Y195       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     1.571 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.193     1.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X107Y193       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     1.778 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.073     1.851    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X107Y190       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.022     1.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.287     2.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X108Y183       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     2.201 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.016     2.217    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y183       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.539ns  (logic 0.532ns (20.953%)  route 2.007ns (79.047%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.681ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.681ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.383     1.765    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[10]
    SLICE_X109Y195       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.015     1.780 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_30/O
                         net (fo=1, routed)           0.051     1.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_30_n_0
    SLICE_X109Y193       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.035     1.866 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.276     2.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X107Y190       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.041     2.183 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.281     2.464    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X108Y182       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.059     2.523 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     2.539    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.951ns  (logic 0.632ns (21.416%)  route 2.319ns (78.584%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        1.683ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.683ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.536ns (routing 0.463ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.413     1.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[14]
    SLICE_X108Y194       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.060     1.890 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_94/O
                         net (fo=1, routed)           0.196     2.086    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_94_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     2.121 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_72/O
                         net (fo=1, routed)           0.073     2.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_72_n_0
    SLICE_X107Y193       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.041     2.235 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.231     2.466    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X109Y192       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.014     2.480 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10/O
                         net (fo=1, routed)           0.234     2.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10_n_0
    SLICE_X107Y185       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.051     2.765 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.146     2.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X107Y176       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     2.925 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     2.951    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.536     1.683    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_pl_0

Max Delay          1752 Endpoints
Min Delay          1752 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.311ns  (logic 0.202ns (8.741%)  route 2.109ns (91.259%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.060ns
    Source Clock Delay      (SCD):    5.232ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.611ns (routing 1.545ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.691ns, distribution 1.187ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.611     5.232    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.311 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=216, routed)         1.783     7.094    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/peripheral_aresetn[0]_bufg_place_replica_1
    SLICE_X51Y228        LUT1 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     7.217 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.326     7.543    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X51Y228        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.878     2.060    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X51Y228        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.373ns  (logic 0.202ns (14.711%)  route 1.171ns (85.289%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.126ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.106ns
    Source Clock Delay      (SCD):    5.232ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.611ns (routing 1.545ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.691ns, distribution 1.233ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.611     5.232    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.311 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=216, routed)         0.834     6.145    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/peripheral_aresetn[0]_bufg_place_replica_1
    SLICE_X49Y284        LUT1 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     6.268 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.337     6.605    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X49Y284        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.924     2.106    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X49Y284        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.133ns  (logic 0.079ns (6.975%)  route 1.054ns (93.025%))
  Logic Levels:           0  
  Clock Path Skew:        -3.219ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.062ns
    Source Clock Delay      (SCD):    5.281ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.660ns (routing 1.545ns, distribution 1.115ns)
  Clock Net Delay (Destination): 1.880ns (routing 0.691ns, distribution 1.189ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.660     5.281    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X50Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y230        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     5.360 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          1.054     6.414    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X53Y224        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.880     2.062    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X53Y224        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.880ns  (logic 0.178ns (20.226%)  route 0.702ns (79.774%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.128ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.104ns
    Source Clock Delay      (SCD):    5.232ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.611ns (routing 1.545ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.691ns, distribution 1.231ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.611     5.232    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X77Y325        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y325        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.311 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=216, routed)         0.555     5.866    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/peripheral_aresetn[0]_bufg_place_replica_1
    SLICE_X50Y329        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     5.965 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.147     6.112    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X50Y329        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.922     2.104    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X50Y329        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.546ns  (logic 0.079ns (14.466%)  route 0.467ns (85.534%))
  Logic Levels:           0  
  Clock Path Skew:        -3.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.115ns
    Source Clock Delay      (SCD):    5.318ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.697ns (routing 1.545ns, distribution 1.152ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.691ns, distribution 1.242ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.697     5.318    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X49Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y281        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.397 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.467     5.864    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X49Y283        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.933     2.115    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X49Y283        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.234ns  (logic 0.079ns (33.756%)  route 0.155ns (66.245%))
  Logic Levels:           0  
  Clock Path Skew:        -3.187ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.117ns
    Source Clock Delay      (SCD):    5.304ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.683ns (routing 1.545ns, distribution 1.138ns)
  Clock Net Delay (Destination): 1.935ns (routing 0.691ns, distribution 1.244ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.683     5.304    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X49Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y332        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.383 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.155     5.538    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X49Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.935     2.117    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X49Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/ADDRARDADDR[11]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.410ns  (logic 0.178ns (5.219%)  route 3.232ns (94.781%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -2.894ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.261ns
    Source Clock Delay      (SCD):    5.155ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.534ns (routing 1.545ns, distribution 0.989ns)
  Clock Net Delay (Destination): 2.079ns (routing 0.691ns, distribution 1.388ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.534     5.155    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X61Y228        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y228        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.232 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/Q
                         net (fo=63, routed)          0.256     5.488    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[3]
    SLICE_X63Y224        LUT5 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.101     5.589 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_4/O
                         net (fo=28, routed)          2.976     8.565    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[8]
    RAMB36_X7Y64         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/ADDRARDADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.079     2.261    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y64         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ADDRARDADDR[11]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.404ns  (logic 0.178ns (5.230%)  route 3.226ns (94.770%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -2.901ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.254ns
    Source Clock Delay      (SCD):    5.155ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.534ns (routing 1.545ns, distribution 0.989ns)
  Clock Net Delay (Destination): 2.072ns (routing 0.691ns, distribution 1.381ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.534     5.155    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X61Y228        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y228        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.232 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/Q
                         net (fo=63, routed)          0.256     5.488    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[3]
    SLICE_X63Y224        LUT5 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.101     5.589 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_4/O
                         net (fo=28, routed)          2.970     8.559    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[8]
    RAMB36_X7Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ADDRARDADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.072     2.254    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ADDRARDADDR[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.375ns  (logic 0.229ns (6.785%)  route 3.146ns (93.215%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -2.897ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.254ns
    Source Clock Delay      (SCD):    5.151ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.530ns (routing 1.545ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.072ns (routing 0.691ns, distribution 1.381ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.530     5.151    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X62Y226        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y226        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.230 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.196     5.426    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X61Y226        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     5.576 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_8/O
                         net (fo=28, routed)          2.950     8.526    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[4]
    RAMB36_X7Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ADDRARDADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.072     2.254    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/ADDRARDADDR[11]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.327ns  (logic 0.178ns (5.351%)  route 3.149ns (94.649%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -2.907ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.248ns
    Source Clock Delay      (SCD):    5.155ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.534ns (routing 1.545ns, distribution 0.989ns)
  Clock Net Delay (Destination): 2.066ns (routing 0.691ns, distribution 1.375ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.249     2.475    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.348 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.593    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.621 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.534     5.155    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X61Y228        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y228        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.232 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[4]/Q
                         net (fo=63, routed)          0.256     5.488    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[3]
    SLICE_X63Y224        LUT5 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.101     5.589 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_4/O
                         net (fo=28, routed)          2.893     8.482    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[8]
    RAMB36_X7Y66         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/ADDRARDADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.066     2.248    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y66         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKARDCLK





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        -1.744ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    3.202ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.453ns (routing 0.846ns, distribution 0.607ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.463ns, distribution 0.848ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.453     3.202    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y232        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     3.242 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.078     3.320    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X50Y231        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.311     1.458    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X50Y231        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        -1.738ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.493ns
    Source Clock Delay      (SCD):    3.231ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.482ns (routing 0.846ns, distribution 0.636ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.463ns, distribution 0.883ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.482     3.231    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X49Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y332        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.270 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.059     3.329    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X49Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.346     1.493    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X49Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -1.743ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.488ns
    Source Clock Delay      (SCD):    3.231ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.482ns (routing 0.846ns, distribution 0.636ns)
  Clock Net Delay (Destination): 1.341ns (routing 0.463ns, distribution 0.878ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.482     3.231    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X49Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y332        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.270 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.060     3.330    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X49Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.341     1.488    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X49Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -1.758ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.463ns
    Source Clock Delay      (SCD):    3.221ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.472ns (routing 0.846ns, distribution 0.626ns)
  Clock Net Delay (Destination): 1.316ns (routing 0.463ns, distribution 0.853ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.472     3.221    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y278        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.260 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.081     3.341    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X51Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.316     1.463    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.773%)  route 0.080ns (67.227%))
  Logic Levels:           0  
  Clock Path Skew:        -1.747ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.476ns
    Source Clock Delay      (SCD):    3.223ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.474ns (routing 0.846ns, distribution 0.628ns)
  Clock Net Delay (Destination): 1.329ns (routing 0.463ns, distribution 0.866ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.474     3.223    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X49Y279        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y279        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.262 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.080     3.342    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X49Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.329     1.476    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X49Y278        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.083%)  route 0.105ns (72.917%))
  Logic Levels:           0  
  Clock Path Skew:        -1.761ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    3.206ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.457ns (routing 0.846ns, distribution 0.611ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.463ns, distribution 0.835ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.457     3.206    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y230        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.245 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.105     3.350    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.298     1.445    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y230        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -1.739ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.493ns
    Source Clock Delay      (SCD):    3.232ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.483ns (routing 0.846ns, distribution 0.637ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.463ns, distribution 0.883ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.483     3.232    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X50Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y333        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.271 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.081     3.352    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X49Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.346     1.493    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X49Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.041ns (31.298%)  route 0.090ns (68.702%))
  Logic Levels:           0  
  Clock Path Skew:        -1.758ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.470ns
    Source Clock Delay      (SCD):    3.228ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.479ns (routing 0.846ns, distribution 0.633ns)
  Clock Net Delay (Destination): 1.323ns (routing 0.463ns, distribution 0.860ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.479     3.228    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X49Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y281        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.269 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.090     3.359    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X49Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.323     1.470    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X49Y281        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.162ns  (logic 0.039ns (24.074%)  route 0.123ns (75.926%))
  Logic Levels:           0  
  Clock Path Skew:        -1.744ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    3.202ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.453ns (routing 0.846ns, distribution 0.607ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.463ns, distribution 0.848ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.453     3.202    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y232        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.241 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.123     3.364    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X50Y231        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.311     1.458    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X50Y231        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.167ns  (logic 0.039ns (23.353%)  route 0.128ns (76.647%))
  Logic Levels:           0  
  Clock Path Skew:        -1.761ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.441ns
    Source Clock Delay      (SCD):    3.202ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.453ns (routing 0.846ns, distribution 0.607ns)
  Clock Net Delay (Destination): 1.294ns (routing 0.463ns, distribution 0.831ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.236     1.356    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.586 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.732    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.749 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.453     3.202    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y232        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.241 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.128     3.369    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.294     1.441    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y232        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay           174 Endpoints
Min Delay           174 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.549ns  (logic 0.079ns (1.424%)  route 5.470ns (98.576%))
  Logic Levels:           0  
  Clock Path Skew:        -0.390ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.197ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.691ns, distribution 1.324ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         5.470     8.137    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X25Y193        FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.015     2.197    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X25Y193        FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.054ns  (logic 0.079ns (1.563%)  route 4.975ns (98.437%))
  Logic Levels:           0  
  Clock Path Skew:        -0.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.149ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.967ns (routing 0.691ns, distribution 1.276ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         4.975     7.642    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X36Y203        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.967     2.149    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X36Y203        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.963ns  (logic 0.079ns (1.592%)  route 4.884ns (98.408%))
  Logic Levels:           0  
  Clock Path Skew:        -0.422ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.166ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.984ns (routing 0.691ns, distribution 1.293ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         4.884     7.551    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X34Y236        FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.984     2.166    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X34Y236        FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.407ns  (logic 0.079ns (2.319%)  route 3.328ns (97.681%))
  Logic Levels:           0  
  Clock Path Skew:        -0.430ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.158ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.976ns (routing 0.691ns, distribution 1.285ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         3.328     5.994    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X37Y233        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.976     2.158    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X37Y233        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.240ns  (logic 0.079ns (2.438%)  route 3.161ns (97.562%))
  Logic Levels:           0  
  Clock Path Skew:        -0.427ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.161ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.979ns (routing 0.691ns, distribution 1.288ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         3.161     5.827    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X35Y220        FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.979     2.161    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X35Y220        FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.954ns  (logic 0.079ns (2.675%)  route 2.875ns (97.325%))
  Logic Levels:           0  
  Clock Path Skew:        -0.489ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.098ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.916ns (routing 0.691ns, distribution 1.225ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         2.875     5.541    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X40Y224        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.916     2.098    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X40Y224        FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.832ns  (logic 0.227ns (8.016%)  route 2.605ns (91.984%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.401ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.187ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.005ns (routing 0.691ns, distribution 1.314ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 f  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         2.384     5.050    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X27Y157        LUT1 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     5.198 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.221     5.419    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    SLICE_X27Y157        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.005     2.187    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
    SLICE_X27Y157        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.657ns  (logic 0.079ns (2.973%)  route 2.578ns (97.027%))
  Logic Levels:           0  
  Clock Path Skew:        -0.518ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.069ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.887ns (routing 0.691ns, distribution 1.196ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         2.578     5.245    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X45Y203        FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.887     2.069    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X45Y203        FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.533ns  (logic 0.079ns (3.118%)  route 2.454ns (96.882%))
  Logic Levels:           0  
  Clock Path Skew:        -0.519ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.068ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.886ns (routing 0.691ns, distribution 1.195ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         2.454     5.121    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X47Y206        FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.886     2.068    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X47Y206        FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.130ns  (logic 0.079ns (3.709%)  route 2.051ns (96.291%))
  Logic Levels:           0  
  Clock Path Skew:        -0.491ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.096ns
    Source Clock Delay      (SCD):    2.587ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.361ns (routing 0.764ns, distribution 1.597ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.691ns, distribution 1.223ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.361     2.587    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y123        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.666 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=139, routed)         2.051     4.718    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X41Y183        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.914     2.096    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X41Y183        FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.135ns  (logic 0.039ns (28.957%)  route 0.096ns (71.043%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.455ns
    Source Clock Delay      (SCD):    1.290ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.170ns (routing 0.414ns, distribution 0.756ns)
  Clock Net Delay (Destination): 1.308ns (routing 0.463ns, distribution 0.845ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.170     1.290    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X47Y195        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y195        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.329 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.096     1.424    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X48Y194        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.308     1.455    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X48Y194        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.181ns  (logic 0.039ns (21.565%)  route 0.142ns (78.435%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    1.292ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.172ns (routing 0.414ns, distribution 0.758ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.463ns, distribution 0.848ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.172     1.292    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X47Y191        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y191        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.331 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.142     1.472    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X47Y195        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.311     1.458    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X47Y195        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.039ns (23.686%)  route 0.126ns (76.314%))
  Logic Levels:           0  
  Clock Path Skew:        0.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.507ns
    Source Clock Delay      (SCD):    1.331ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.211ns (routing 0.414ns, distribution 0.797ns)
  Clock Net Delay (Destination): 1.360ns (routing 0.463ns, distribution 0.897ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.211     1.331    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X34Y216        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y216        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.370 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.126     1.495    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X34Y216        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.360     1.507    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X34Y216        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.150ns  (logic 0.038ns (25.300%)  route 0.112ns (74.700%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.532ns
    Source Clock Delay      (SCD):    1.351ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.231ns (routing 0.414ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.385ns (routing 0.463ns, distribution 0.922ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.231     1.351    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X27Y153        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y153        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.389 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.112     1.501    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X27Y154        FDCE                                         f  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.385     1.532    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X27Y154        FDCE                                         r  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.150ns  (logic 0.038ns (25.300%)  route 0.112ns (74.700%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.532ns
    Source Clock Delay      (SCD):    1.351ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.231ns (routing 0.414ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.385ns (routing 0.463ns, distribution 0.922ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.231     1.351    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X27Y153        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y153        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.389 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.112     1.501    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X27Y154        FDCE                                         f  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.385     1.532    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X27Y154        FDCE                                         r  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.150ns  (logic 0.038ns (25.300%)  route 0.112ns (74.700%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.532ns
    Source Clock Delay      (SCD):    1.351ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.231ns (routing 0.414ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.385ns (routing 0.463ns, distribution 0.922ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.231     1.351    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X27Y153        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y153        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.389 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.112     1.501    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X27Y154        FDCE                                         f  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.385     1.532    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X27Y154        FDCE                                         r  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.041ns (30.217%)  route 0.095ns (69.783%))
  Logic Levels:           0  
  Clock Path Skew:        0.185ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.564ns
    Source Clock Delay      (SCD):    1.380ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.260ns (routing 0.414ns, distribution 0.846ns)
  Clock Net Delay (Destination): 1.417ns (routing 0.463ns, distribution 0.954ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.260     1.380    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X70Y310        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y310        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.421 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.095     1.515    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X70Y306        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.417     1.564    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X70Y306        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.038ns (21.392%)  route 0.140ns (78.608%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.533ns
    Source Clock Delay      (SCD):    1.351ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.231ns (routing 0.414ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.386ns (routing 0.463ns, distribution 0.923ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.231     1.351    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X27Y153        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y153        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.389 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.140     1.528    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X27Y156        FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.386     1.533    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X27Y156        FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.038ns (21.392%)  route 0.140ns (78.608%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.533ns
    Source Clock Delay      (SCD):    1.351ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.231ns (routing 0.414ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.386ns (routing 0.463ns, distribution 0.923ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.231     1.351    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X27Y153        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y153        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.389 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.140     1.528    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X27Y156        FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.386     1.533    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X27Y156        FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.038ns (21.392%)  route 0.140ns (78.608%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.533ns
    Source Clock Delay      (SCD):    1.351ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.231ns (routing 0.414ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.386ns (routing 0.463ns, distribution 0.923ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.231     1.351    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X27Y153        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y153        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.389 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.140     1.528    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X27Y156        FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.386     1.533    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X27Y156        FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay            94 Endpoints
Min Delay           102 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[0]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.729ns  (logic 0.078ns (10.696%)  route 0.651ns (89.304%))
  Logic Levels:           0  
  Clock Path Skew:        2.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.952ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.424ns (routing 1.653ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.651     3.614    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X97Y7          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.424     4.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X97Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[1]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.729ns  (logic 0.078ns (10.696%)  route 0.651ns (89.304%))
  Logic Levels:           0  
  Clock Path Skew:        2.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.952ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.424ns (routing 1.653ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.651     3.614    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X97Y7          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.424     4.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X97Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[2]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.729ns  (logic 0.078ns (10.696%)  route 0.651ns (89.304%))
  Logic Levels:           0  
  Clock Path Skew:        2.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.952ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.424ns (routing 1.653ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.651     3.614    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X97Y7          FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.424     4.952    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X97Y7          FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.713ns  (logic 0.078ns (10.937%)  route 0.635ns (89.063%))
  Logic Levels:           0  
  Clock Path Skew:        2.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.947ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.419ns (routing 1.653ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.635     3.598    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.419     4.947    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.713ns  (logic 0.078ns (10.937%)  route 0.635ns (89.063%))
  Logic Levels:           0  
  Clock Path Skew:        2.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.947ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.419ns (routing 1.653ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.635     3.598    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.419     4.947    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.713ns  (logic 0.078ns (10.937%)  route 0.635ns (89.063%))
  Logic Levels:           0  
  Clock Path Skew:        2.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.947ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.419ns (routing 1.653ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.635     3.598    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.419     4.947    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.713ns  (logic 0.078ns (10.937%)  route 0.635ns (89.063%))
  Logic Levels:           0  
  Clock Path Skew:        2.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.947ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.419ns (routing 1.653ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.635     3.598    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[9]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.419     4.947    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[9]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.712ns  (logic 0.078ns (10.953%)  route 0.634ns (89.048%))
  Logic Levels:           0  
  Clock Path Skew:        2.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.949ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.421ns (routing 1.653ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.634     3.597    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[13]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.421     4.949    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.712ns  (logic 0.078ns (10.953%)  route 0.634ns (89.048%))
  Logic Levels:           0  
  Clock Path Skew:        2.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.949ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.421ns (routing 1.653ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.634     3.597    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[14]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.421     4.949    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[14]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.712ns  (logic 0.078ns (10.953%)  route 0.634ns (89.048%))
  Logic Levels:           0  
  Clock Path Skew:        2.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.949ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.677ns (routing 0.773ns, distribution 0.904ns)
  Clock Net Delay (Destination): 2.421ns (routing 1.653ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     1.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.208 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.677     2.884    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y13         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.962 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.634     3.597    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/RST_I
    SLICE_X98Y10         FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.421     4.949    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X98Y10         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_reg_in_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.094ns  (logic 0.039ns (41.489%)  route 0.055ns (58.511%))
  Logic Levels:           0  
  Clock Path Skew:        6.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.141ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.916ns (routing 0.426ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.696ns (routing 1.125ns, distribution 0.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.916     1.915    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9         FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.954 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.055     2.009    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X100Y8         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.696     8.141    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X100Y8         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        6.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.137ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.916ns (routing 0.426ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.692ns (routing 1.125ns, distribution 0.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.916     1.915    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9         FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.954 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.057     2.011    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X100Y8         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.692     8.137    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X100Y8         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.224ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.132ns
    Source Clock Delay      (SCD):    1.908ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.909ns (routing 0.426ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.687ns (routing 1.125ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.909     1.908    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X100Y19        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y19        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.948 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     2.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[0]
    SLICE_X100Y20        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.687     8.132    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X100Y20        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        6.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.137ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.916ns (routing 0.426ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.692ns (routing 1.125ns, distribution 0.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.916     1.915    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y9         FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.954 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.079     2.033    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.692     8.137    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X100Y9         FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.220ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.135ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.916ns (routing 0.426ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.690ns (routing 1.125ns, distribution 0.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.916     1.915    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X101Y17        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y17        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.955 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.079     2.034    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[2]
    SLICE_X101Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.690     8.135    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X101Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.220ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.135ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.916ns (routing 0.426ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.690ns (routing 1.125ns, distribution 0.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.916     1.915    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X102Y17        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y17        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.955 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.079     2.034    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[2]
    SLICE_X102Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.690     8.135    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X102Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        6.216ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.130ns
    Source Clock Delay      (SCD):    1.914ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.915ns (routing 0.426ns, distribution 0.489ns)
  Clock Net Delay (Destination): 1.685ns (routing 1.125ns, distribution 0.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.915     1.914    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X100Y16        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y16        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.954 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.080     2.034    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[0]
    SLICE_X100Y17        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.685     8.130    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X100Y17        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.212ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.128ns
    Source Clock Delay      (SCD):    1.916ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.917ns (routing 0.426ns, distribution 0.491ns)
  Clock Net Delay (Destination): 1.683ns (routing 1.125ns, distribution 0.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.917     1.916    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X101Y15        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y15        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.956 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.079     2.035    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[1]
    SLICE_X101Y16        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.683     8.128    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X101Y16        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        6.217ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.135ns
    Source Clock Delay      (SCD):    1.919ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.919ns (routing 0.426ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.690ns (routing 1.125ns, distribution 0.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.919     1.919    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X100Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y14        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.959 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.079     2.038    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[1]
    SLICE_X100Y15        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.690     8.135    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X100Y15        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/ma_rst_1_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.115ns  (logic 0.039ns (33.926%)  route 0.076ns (66.074%))
  Logic Levels:           0  
  Clock Path Skew:        6.205ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.129ns
    Source Clock Delay      (SCD):    1.924ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.924ns (routing 0.426ns, distribution 0.498ns)
  Clock Net Delay (Destination): 1.684ns (routing 1.125ns, distribution 0.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.924     1.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.963 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.076     2.038    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/ma_rst
    SLICE_X97Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/ma_rst_1_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.684     8.129    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X97Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/ma_rst_1_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  default_sysclk_c0_300mhz_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (recovery check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.345ns  (logic 0.079ns (22.899%)  route 0.266ns (77.101%))
  Logic Levels:           0  
  Clock Path Skew:        -1.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.503ns
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 0.638ns (routing 0.001ns, distribution 0.637ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y116        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.266     2.954    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y113        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.841    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.865 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.638     1.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (recovery check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.345ns  (logic 0.079ns (22.899%)  route 0.266ns (77.101%))
  Logic Levels:           0  
  Clock Path Skew:        -1.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.503ns
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.383ns (routing 0.764ns, distribution 1.619ns)
  Clock Net Delay (Destination): 0.638ns (routing 0.001ns, distribution 0.637ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.383     2.609    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y116        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.266     2.954    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y113        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.841    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.865 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.638     1.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (removal check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.039ns (24.684%)  route 0.119ns (75.316%))
  Logic Levels:           0  
  Clock Path Skew:        -0.175ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.254ns
    Source Clock Delay      (SCD):    1.429ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.309ns (routing 0.414ns, distribution 0.895ns)
  Clock Net Delay (Destination): 0.474ns (routing 0.001ns, distribution 0.473ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.309     1.429    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y116        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.468 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.119     1.587    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y113        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.474     1.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (removal check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.039ns (24.684%)  route 0.119ns (75.316%))
  Logic Levels:           0  
  Clock Path Skew:        -0.175ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.254ns
    Source Clock Delay      (SCD):    1.429ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.309ns (routing 0.414ns, distribution 0.895ns)
  Clock Net Delay (Destination): 0.474ns (routing 0.001ns, distribution 0.473ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.309     1.429    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y116        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.468 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.119     1.587    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y113        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.474     1.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X81Y113        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  mmcm_clkout0

Max Delay           262 Endpoints
Min Delay           262 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[208]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.996ns  (logic 0.281ns (28.213%)  route 0.715ns (71.787%))
  Logic Levels:           0  
  Clock Path Skew:        0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    2.886ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.360ns (routing 1.062ns, distribution 1.298ns)
  Clock Net Delay (Destination): 1.583ns (routing 0.695ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.360     2.886    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/WCLK
    SLICE_X63Y99         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y99         RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     3.167 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMG/O
                         net (fo=1, routed)           0.715     3.882    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[208]
    SLICE_X66Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[208]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.583     3.342    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X66Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[208]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[207]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.967ns  (logic 0.304ns (31.437%)  route 0.663ns (68.563%))
  Logic Levels:           0  
  Clock Path Skew:        0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    2.886ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.360ns (routing 1.062ns, distribution 1.298ns)
  Clock Net Delay (Destination): 1.583ns (routing 0.695ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.360     2.886    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/WCLK
    SLICE_X63Y99         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y99         RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     3.190 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMF_D1/O
                         net (fo=1, routed)           0.663     3.853    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[207]
    SLICE_X67Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[207]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.583     3.342    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X67Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[207]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[212]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.856ns  (logic 0.292ns (34.112%)  route 0.564ns (65.888%))
  Logic Levels:           0  
  Clock Path Skew:        0.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    2.909ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.383ns (routing 1.062ns, distribution 1.321ns)
  Clock Net Delay (Destination): 1.583ns (routing 0.695ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.383     2.909    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/WCLK
    SLICE_X66Y101        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y101        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     3.201 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMB/O
                         net (fo=1, routed)           0.564     3.765    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[212]
    SLICE_X67Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[212]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.583     3.342    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X67Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[212]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[198]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.845ns  (logic 0.292ns (34.556%)  route 0.553ns (65.444%))
  Logic Levels:           0  
  Clock Path Skew:        0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    2.886ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.360ns (routing 1.062ns, distribution 1.298ns)
  Clock Net Delay (Destination): 1.583ns (routing 0.695ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.360     2.886    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/WCLK
    SLICE_X63Y99         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y99         RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     3.178 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMB/O
                         net (fo=1, routed)           0.553     3.731    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[198]
    SLICE_X67Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[198]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.583     3.342    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X67Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[198]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[142]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.805ns  (logic 0.292ns (36.273%)  route 0.513ns (63.727%))
  Logic Levels:           0  
  Clock Path Skew:        0.438ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    2.904ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.378ns (routing 1.062ns, distribution 1.316ns)
  Clock Net Delay (Destination): 1.583ns (routing 0.695ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.378     2.904    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/WCLK
    SLICE_X66Y97         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y97         RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     3.196 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMB/O
                         net (fo=1, routed)           0.513     3.709    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[142]
    SLICE_X63Y96         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[142]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.583     3.342    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X63Y96         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[142]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[200]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.814ns  (logic 0.288ns (35.381%)  route 0.526ns (64.619%))
  Logic Levels:           0  
  Clock Path Skew:        0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    2.886ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.360ns (routing 1.062ns, distribution 1.298ns)
  Clock Net Delay (Destination): 1.583ns (routing 0.695ns, distribution 0.888ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.360     2.886    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/WCLK
    SLICE_X63Y99         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y99         RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     3.174 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAMC/O
                         net (fo=1, routed)           0.526     3.700    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[200]
    SLICE_X66Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[200]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.583     3.342    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X66Y99         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[200]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[148]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.764ns  (logic 0.288ns (37.696%)  route 0.476ns (62.304%))
  Logic Levels:           0  
  Clock Path Skew:        0.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.337ns
    Source Clock Delay      (SCD):    2.904ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.378ns (routing 1.062ns, distribution 1.316ns)
  Clock Net Delay (Destination): 1.578ns (routing 0.695ns, distribution 0.883ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.378     2.904    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/WCLK
    SLICE_X66Y97         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y97         RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     3.192 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAME/O
                         net (fo=1, routed)           0.476     3.668    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[148]
    SLICE_X64Y95         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[148]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.578     3.337    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y95         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[148]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[100]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.840ns  (logic 0.292ns (34.762%)  route 0.548ns (65.238%))
  Logic Levels:           0  
  Clock Path Skew:        0.576ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.397ns
    Source Clock Delay      (SCD):    2.821ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.295ns (routing 1.062ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.638ns (routing 0.695ns, distribution 0.943ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.295     2.821    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X54Y100        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y100        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     3.113 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB/O
                         net (fo=1, routed)           0.548     3.661    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[100]
    SLICE_X55Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[100]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.638     3.397    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[100]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[169]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.760ns  (logic 0.305ns (40.132%)  route 0.455ns (59.868%))
  Logic Levels:           0  
  Clock Path Skew:        0.448ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.347ns
    Source Clock Delay      (SCD):    2.899ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.373ns (routing 1.062ns, distribution 1.311ns)
  Clock Net Delay (Destination): 1.588ns (routing 0.695ns, distribution 0.893ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.373     2.899    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/WCLK
    SLICE_X66Y89         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y89         RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     3.204 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAMA_D1/O
                         net (fo=1, routed)           0.455     3.659    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[169]
    SLICE_X64Y88         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[169]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.588     3.347    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y88         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[169]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[144]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.753ns  (logic 0.288ns (38.247%)  route 0.465ns (61.753%))
  Logic Levels:           0  
  Clock Path Skew:        0.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.343ns
    Source Clock Delay      (SCD):    2.904ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.378ns (routing 1.062ns, distribution 1.316ns)
  Clock Net Delay (Destination): 1.584ns (routing 0.695ns, distribution 0.889ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       2.378     2.904    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/WCLK
    SLICE_X66Y97         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y97         RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     3.192 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMC/O
                         net (fo=1, routed)           0.465     3.657    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[144]
    SLICE_X63Y97         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[144]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.584     3.343    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X63Y97         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[144]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.706%)  route 0.080ns (67.294%))
  Logic Levels:           0  
  Clock Path Skew:        0.327ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.832ns
    Source Clock Delay      (SCD):    1.505ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.243ns (routing 0.578ns, distribution 0.665ns)
  Clock Net Delay (Destination): 1.169ns (routing 0.473ns, distribution 0.696ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.243     1.505    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X50Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y103        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.544 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.080     1.624    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X51Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.169     1.832    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X51Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.156ns  (logic 0.039ns (25.000%)  route 0.117ns (75.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.324ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.832ns
    Source Clock Delay      (SCD):    1.508ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.246ns (routing 0.578ns, distribution 0.668ns)
  Clock Net Delay (Destination): 1.169ns (routing 0.473ns, distribution 0.696ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.246     1.508    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y103        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.547 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.117     1.664    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X51Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.169     1.832    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.177ns  (logic 0.039ns (22.034%)  route 0.138ns (77.966%))
  Logic Levels:           0  
  Clock Path Skew:        0.339ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.839ns
    Source Clock Delay      (SCD):    1.500ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.238ns (routing 0.578ns, distribution 0.660ns)
  Clock Net Delay (Destination): 1.176ns (routing 0.473ns, distribution 0.703ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.238     1.500    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y101        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.539 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.138     1.677    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.176     1.839    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.039ns (21.910%)  route 0.139ns (78.090%))
  Logic Levels:           0  
  Clock Path Skew:        0.339ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.839ns
    Source Clock Delay      (SCD):    1.500ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.238ns (routing 0.578ns, distribution 0.660ns)
  Clock Net Delay (Destination): 1.176ns (routing 0.473ns, distribution 0.703ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.238     1.500    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y101        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.539 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.139     1.678    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.176     1.839    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.040ns (21.858%)  route 0.143ns (78.142%))
  Logic Levels:           0  
  Clock Path Skew:        0.343ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.843ns
    Source Clock Delay      (SCD):    1.500ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.238ns (routing 0.578ns, distribution 0.660ns)
  Clock Net Delay (Destination): 1.180ns (routing 0.473ns, distribution 0.707ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.238     1.500    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y101        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.540 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.143     1.683    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.180     1.843    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X51Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[37]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.167ns  (logic 0.108ns (64.671%)  route 0.059ns (35.329%))
  Logic Levels:           0  
  Clock Path Skew:        0.302ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.822ns
    Source Clock Delay      (SCD):    1.520ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.258ns (routing 0.578ns, distribution 0.680ns)
  Clock Net Delay (Destination): 1.159ns (routing 0.473ns, distribution 0.686ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.258     1.520    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X53Y89         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y89         RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     1.628 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME_D1/O
                         net (fo=1, routed)           0.059     1.687    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[37]
    SLICE_X52Y89         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[37]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.159     1.822    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y89         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[37]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[105]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.164ns  (logic 0.111ns (67.683%)  route 0.053ns (32.317%))
  Logic Levels:           0  
  Clock Path Skew:        0.297ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.821ns
    Source Clock Delay      (SCD):    1.524ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.262ns (routing 0.578ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.158ns (routing 0.473ns, distribution 0.685ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.262     1.524    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X54Y100        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y100        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     1.635 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMD_D1/O
                         net (fo=1, routed)           0.053     1.688    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[105]
    SLICE_X55Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[105]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.158     1.821    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[105]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.188ns  (logic 0.039ns (20.745%)  route 0.149ns (79.255%))
  Logic Levels:           0  
  Clock Path Skew:        0.327ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.827ns
    Source Clock Delay      (SCD):    1.500ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.238ns (routing 0.578ns, distribution 0.660ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.473ns, distribution 0.691ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.238     1.500    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X51Y101        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y101        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.539 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.149     1.688    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.164     1.827    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X52Y100        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[117]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.110ns (64.706%)  route 0.060ns (35.294%))
  Logic Levels:           0  
  Clock Path Skew:        0.293ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.813ns
    Source Clock Delay      (SCD):    1.520ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.258ns (routing 0.578ns, distribution 0.680ns)
  Clock Net Delay (Destination): 1.150ns (routing 0.473ns, distribution 0.677ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.258     1.520    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X60Y93         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y93         RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     1.630 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMC_D1/O
                         net (fo=1, routed)           0.060     1.690    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[117]
    SLICE_X60Y94         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[117]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.150     1.813    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y94         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[117]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@2.034ns period=4.069ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[115]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.110ns (63.953%)  route 0.062ns (36.047%))
  Logic Levels:           0  
  Clock Path Skew:        0.293ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.813ns
    Source Clock Delay      (SCD):    1.520ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.258ns (routing 0.578ns, distribution 0.680ns)
  Clock Net Delay (Destination): 1.150ns (routing 0.473ns, distribution 0.677ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=42374, routed)       1.258     1.520    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X60Y93         RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y93         RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     1.630 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB_D1/O
                         net (fo=1, routed)           0.062     1.692    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[115]
    SLICE_X60Y94         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[115]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.150     1.813    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y94         FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[115]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.817ns  (logic 0.079ns (4.347%)  route 1.738ns (95.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.714ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.388ns
    Source Clock Delay      (SCD):    4.102ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      3.391ns (routing 1.864ns, distribution 1.527ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.695ns, distribution 0.934ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.391     4.102    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y247        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.181 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           1.738     5.919    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X57Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.629     3.388    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X57Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.915ns  (logic 0.039ns (4.262%)  route 0.876ns (95.738%))
  Logic Levels:           0  
  Clock Path Skew:        -0.398ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.817ns
    Source Clock Delay      (SCD):    2.215ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.848ns (routing 1.007ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.154ns (routing 0.473ns, distribution 0.681ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      1.848     2.215    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y247        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.254 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.876     3.130    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X57Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.154     1.817    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X57Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  mmcm_clkout0

Max Delay           106 Endpoints
Min Delay           106 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.962ns  (logic 0.081ns (8.422%)  route 0.881ns (91.578%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.415ns
    Source Clock Delay      (SCD):    2.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.144ns (routing 0.764ns, distribution 1.380ns)
  Clock Net Delay (Destination): 1.656ns (routing 0.695ns, distribution 0.961ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.144     2.370    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y107        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y107        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.451 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[31]/Q
                         net (fo=2, routed)           0.881     3.332    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[31]
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.656     3.415    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.901ns  (logic 0.080ns (8.879%)  route 0.821ns (91.121%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.415ns
    Source Clock Delay      (SCD):    2.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.144ns (routing 0.764ns, distribution 1.380ns)
  Clock Net Delay (Destination): 1.656ns (routing 0.695ns, distribution 0.961ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.144     2.370    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y107        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y107        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     2.450 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[27]/Q
                         net (fo=2, routed)           0.821     3.271    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[27]
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.656     3.415    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[27]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.805ns  (logic 0.079ns (9.816%)  route 0.726ns (90.184%))
  Logic Levels:           0  
  Clock Path Skew:        1.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.421ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.157ns (routing 0.764ns, distribution 1.393ns)
  Clock Net Delay (Destination): 1.662ns (routing 0.695ns, distribution 0.967ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.157     2.383    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X44Y102        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y102        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.462 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[22]/Q
                         net (fo=2, routed)           0.726     3.188    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[22]
    SLICE_X45Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.662     3.421    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X45Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.785ns  (logic 0.079ns (10.062%)  route 0.706ns (89.938%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.415ns
    Source Clock Delay      (SCD):    2.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.144ns (routing 0.764ns, distribution 1.380ns)
  Clock Net Delay (Destination): 1.656ns (routing 0.695ns, distribution 0.961ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.144     2.370    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y107        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y107        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.449 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[24]/Q
                         net (fo=2, routed)           0.706     3.155    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[24]
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.656     3.415    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[24]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.733ns  (logic 0.079ns (10.777%)  route 0.654ns (89.223%))
  Logic Levels:           0  
  Clock Path Skew:        1.042ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.427ns
    Source Clock Delay      (SCD):    2.385ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.159ns (routing 0.764ns, distribution 1.395ns)
  Clock Net Delay (Destination): 1.668ns (routing 0.695ns, distribution 0.973ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.159     2.385    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X44Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y104        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.464 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[24]/Q
                         net (fo=2, routed)           0.654     3.118    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[24]
    SLICE_X44Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.668     3.427    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X44Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[24]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.714ns  (logic 0.079ns (11.071%)  route 0.635ns (88.929%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.424ns
    Source Clock Delay      (SCD):    2.379ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.153ns (routing 0.764ns, distribution 1.389ns)
  Clock Net Delay (Destination): 1.665ns (routing 0.695ns, distribution 0.970ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.153     2.379    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y99         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.458 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[2]/Q
                         net (fo=2, routed)           0.635     3.093    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[2]
    SLICE_X49Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.665     3.424    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.718ns  (logic 0.081ns (11.278%)  route 0.637ns (88.722%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.415ns
    Source Clock Delay      (SCD):    2.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.144ns (routing 0.764ns, distribution 1.380ns)
  Clock Net Delay (Destination): 1.656ns (routing 0.695ns, distribution 0.961ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.144     2.370    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y107        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y107        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.451 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/Q
                         net (fo=2, routed)           0.637     3.088    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[25]
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.656     3.415    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.671ns  (logic 0.079ns (11.775%)  route 0.592ns (88.225%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.415ns
    Source Clock Delay      (SCD):    2.370ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.144ns (routing 0.764ns, distribution 1.380ns)
  Clock Net Delay (Destination): 1.656ns (routing 0.695ns, distribution 0.961ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.144     2.370    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y107        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y107        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.449 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/Q
                         net (fo=2, routed)           0.592     3.041    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[28]
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.656     3.415    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y93         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.626ns  (logic 0.081ns (12.946%)  route 0.545ns (87.054%))
  Logic Levels:           0  
  Clock Path Skew:        1.042ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.427ns
    Source Clock Delay      (SCD):    2.385ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.159ns (routing 0.764ns, distribution 1.395ns)
  Clock Net Delay (Destination): 1.668ns (routing 0.695ns, distribution 0.973ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.159     2.385    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X44Y104        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y104        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.466 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[27]/Q
                         net (fo=2, routed)           0.545     3.011    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[27]
    SLICE_X44Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.668     3.427    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X44Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[27]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.631ns  (logic 0.079ns (12.519%)  route 0.552ns (87.481%))
  Logic Levels:           0  
  Clock Path Skew:        1.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.424ns
    Source Clock Delay      (SCD):    2.379ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.153ns (routing 0.764ns, distribution 1.389ns)
  Clock Net Delay (Destination): 1.665ns (routing 0.695ns, distribution 0.970ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.153     2.379    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y99         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.458 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/Q
                         net (fo=2, routed)           0.552     3.010    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[4]
    SLICE_X49Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.665     3.424    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.872%)  route 0.082ns (67.128%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.833ns
    Source Clock Delay      (SCD):    1.294ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.174ns (routing 0.414ns, distribution 0.760ns)
  Clock Net Delay (Destination): 1.170ns (routing 0.473ns, distribution 0.697ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.174     1.294    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y92         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.334 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[2]/Q
                         net (fo=2, routed)           0.082     1.416    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[2]
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.170     1.833    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.702%)  route 0.082ns (67.297%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.833ns
    Source Clock Delay      (SCD):    1.294ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.174ns (routing 0.414ns, distribution 0.760ns)
  Clock Net Delay (Destination): 1.170ns (routing 0.473ns, distribution 0.697ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.174     1.294    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y92         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.334 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/Q
                         net (fo=2, routed)           0.082     1.416    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[6]
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.170     1.833    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.175%)  route 0.081ns (66.825%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.835ns
    Source Clock Delay      (SCD):    1.296ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.176ns (routing 0.414ns, distribution 0.762ns)
  Clock Net Delay (Destination): 1.172ns (routing 0.473ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.176     1.296    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y95         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.336 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/Q
                         net (fo=2, routed)           0.081     1.417    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[11]
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.172     1.835    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (32.050%)  route 0.083ns (67.950%))
  Logic Levels:           0  
  Clock Path Skew:        0.532ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.827ns
    Source Clock Delay      (SCD):    1.295ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.175ns (routing 0.414ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.473ns, distribution 0.691ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.175     1.295    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y92         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.334 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/Q
                         net (fo=2, routed)           0.083     1.417    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[6]
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.164     1.827    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.040ns (32.370%)  route 0.084ns (67.630%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.835ns
    Source Clock Delay      (SCD):    1.296ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.176ns (routing 0.414ns, distribution 0.762ns)
  Clock Net Delay (Destination): 1.172ns (routing 0.473ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.176     1.296    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y95         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.336 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[15]/Q
                         net (fo=2, routed)           0.084     1.420    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[15]
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.172     1.835    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.040ns (32.081%)  route 0.085ns (67.919%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.834ns
    Source Clock Delay      (SCD):    1.295ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.175ns (routing 0.414ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.171ns (routing 0.473ns, distribution 0.698ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.175     1.295    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y92         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.335 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/Q
                         net (fo=2, routed)           0.085     1.420    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[1]
    SLICE_X49Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.171     1.834    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y91         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        0.532ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.827ns
    Source Clock Delay      (SCD):    1.295ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.175ns (routing 0.414ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.473ns, distribution 0.691ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.175     1.295    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y92         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.334 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[2]/Q
                         net (fo=2, routed)           0.087     1.421    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[2]
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.164     1.827    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.307%)  route 0.090ns (69.693%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.833ns
    Source Clock Delay      (SCD):    1.294ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.174ns (routing 0.414ns, distribution 0.760ns)
  Clock Net Delay (Destination): 1.170ns (routing 0.473ns, distribution 0.697ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.174     1.294    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y92         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.333 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[1]/Q
                         net (fo=2, routed)           0.090     1.423    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[1]
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.170     1.833    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X47Y92         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.038ns (31.290%)  route 0.083ns (68.710%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.841ns
    Source Clock Delay      (SCD):    1.302ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.182ns (routing 0.414ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.178ns (routing 0.473ns, distribution 0.705ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.182     1.302    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X48Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y99         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.340 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[16]/Q
                         net (fo=2, routed)           0.083     1.423    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[16]
    SLICE_X48Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.178     1.841    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X48Y99         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[16]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.041ns (32.262%)  route 0.086ns (67.739%))
  Logic Levels:           0  
  Clock Path Skew:        0.539ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.835ns
    Source Clock Delay      (SCD):    1.296ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.176ns (routing 0.414ns, distribution 0.762ns)
  Clock Net Delay (Destination): 1.172ns (routing 0.473ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.176     1.296    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y95         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.337 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/Q
                         net (fo=2, routed)           0.086     1.423    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[9]
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.172     1.835    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y95         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  default_sysclk_c0_300mhz_clk_p
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.291ns  (logic 0.081ns (27.832%)  route 0.210ns (72.168%))
  Logic Levels:           0  
  Clock Path Skew:        1.380ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.180ns
    Source Clock Delay      (SCD):    1.801ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.768ns (routing 0.001ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.421ns (routing 0.695ns, distribution 0.726ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.768     1.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y103        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     1.882 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.210     2.092    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X95Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.421     3.180    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X95Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.040ns (32.604%)  route 0.083ns (67.396%))
  Logic Levels:           0  
  Clock Path Skew:        0.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    1.039ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.432ns (routing 0.000ns, distribution 0.432ns)
  Clock Net Delay (Destination): 1.012ns (routing 0.473ns, distribution 0.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.432     1.039    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y103        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.083     1.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X95Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.012     1.675    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X95Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Max Delay            68 Endpoints
Min Delay            68 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.192ns  (logic 0.079ns (3.603%)  route 2.113ns (96.397%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.461ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.695ns, distribution 1.007ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.113     5.261    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X34Y53         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.702     3.461    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X34Y53         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.192ns  (logic 0.079ns (3.603%)  route 2.113ns (96.397%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.461ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.695ns, distribution 1.007ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.113     5.261    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X34Y53         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.702     3.461    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X34Y53         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.192ns  (logic 0.079ns (3.603%)  route 2.113ns (96.397%))
  Logic Levels:           0  
  Clock Path Skew:        0.393ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.461ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.695ns, distribution 1.007ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.113     5.261    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X34Y53         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.702     3.461    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X34Y53         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.092ns  (logic 0.079ns (3.775%)  route 2.013ns (96.225%))
  Logic Levels:           0  
  Clock Path Skew:        0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.280ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.521ns (routing 0.695ns, distribution 0.826ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.013     5.161    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X78Y43         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.521     3.280    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X78Y43         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.092ns  (logic 0.079ns (3.775%)  route 2.013ns (96.225%))
  Logic Levels:           0  
  Clock Path Skew:        0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.280ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.521ns (routing 0.695ns, distribution 0.826ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.013     5.161    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X78Y43         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.521     3.280    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X78Y43         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.092ns  (logic 0.079ns (3.775%)  route 2.013ns (96.225%))
  Logic Levels:           0  
  Clock Path Skew:        0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.280ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.521ns (routing 0.695ns, distribution 0.826ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.013     5.161    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X78Y43         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.521     3.280    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X78Y43         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.089ns  (logic 0.079ns (3.781%)  route 2.010ns (96.219%))
  Logic Levels:           0  
  Clock Path Skew:        0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.279ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.520ns (routing 0.695ns, distribution 0.825ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.010     5.158    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X78Y43         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.520     3.279    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X78Y43         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.089ns  (logic 0.079ns (3.781%)  route 2.010ns (96.219%))
  Logic Levels:           0  
  Clock Path Skew:        0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.279ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.520ns (routing 0.695ns, distribution 0.825ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.010     5.158    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X78Y43         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.520     3.279    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X78Y43         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.089ns  (logic 0.079ns (3.781%)  route 2.010ns (96.219%))
  Logic Levels:           0  
  Clock Path Skew:        0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.279ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.520ns (routing 0.695ns, distribution 0.825ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.010     5.158    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X78Y43         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.520     3.279    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X78Y43         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        1.866ns  (logic 0.079ns (4.235%)  route 1.787ns (95.765%))
  Logic Levels:           0  
  Clock Path Skew:        0.224ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.293ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.852ns (routing 0.764ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.534ns (routing 0.695ns, distribution 0.839ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.852     3.069    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.148 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.787     4.934    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X74Y48         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.735    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.759 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.534     3.293    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X74Y48         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.355ns  (logic 0.040ns (11.268%)  route 0.315ns (88.732%))
  Logic Levels:           0  
  Clock Path Skew:        -0.147ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.757ns
    Source Clock Delay      (SCD):    1.904ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.899ns (routing 0.421ns, distribution 0.478ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.473ns, distribution 0.621ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.899     1.904    d_1_i/ddr4/ddr4_0/inst/c0_ddr4_ui_clk
    SLICE_X81Y86         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y86         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.944 r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/Q
                         net (fo=1, routed)           0.315     2.259    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X79Y87         FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.094     1.757    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X79Y87         FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.308ns  (logic 0.039ns (12.677%)  route 0.269ns (87.323%))
  Logic Levels:           0  
  Clock Path Skew:        -0.201ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.827ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.473ns, distribution 0.691ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.269     2.336    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y90         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.164     1.827    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y90         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.308ns  (logic 0.039ns (12.677%)  route 0.269ns (87.323%))
  Logic Levels:           0  
  Clock Path Skew:        -0.201ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.827ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.473ns, distribution 0.691ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.269     2.336    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y90         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.164     1.827    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y90         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.308ns  (logic 0.039ns (12.677%)  route 0.269ns (87.323%))
  Logic Levels:           0  
  Clock Path Skew:        -0.201ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.827ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.473ns, distribution 0.691ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.269     2.336    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X50Y90         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.164     1.827    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X50Y90         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.384ns  (logic 0.039ns (10.153%)  route 0.345ns (89.847%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.836ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.173ns (routing 0.473ns, distribution 0.700ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.345     2.412    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X49Y79         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.173     1.836    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X49Y79         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.384ns  (logic 0.039ns (10.153%)  route 0.345ns (89.847%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.836ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.173ns (routing 0.473ns, distribution 0.700ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.345     2.412    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X49Y79         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.173     1.836    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X49Y79         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.384ns  (logic 0.039ns (10.153%)  route 0.345ns (89.847%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.836ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.173ns (routing 0.473ns, distribution 0.700ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.345     2.412    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X49Y79         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.173     1.836    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X49Y79         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.501ns  (logic 0.039ns (7.777%)  route 0.462ns (92.223%))
  Logic Levels:           0  
  Clock Path Skew:        -0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.861ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.199ns (routing 0.473ns, distribution 0.726ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.462     2.529    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X42Y82         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.199     1.861    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X42Y82         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.501ns  (logic 0.039ns (7.777%)  route 0.462ns (92.223%))
  Logic Levels:           0  
  Clock Path Skew:        -0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.861ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.199ns (routing 0.473ns, distribution 0.726ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.462     2.529    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X42Y82         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.199     1.861    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X42Y82         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.501ns  (logic 0.039ns (7.777%)  route 0.462ns (92.223%))
  Logic Levels:           0  
  Clock Path Skew:        -0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.861ns
    Source Clock Delay      (SCD):    2.028ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.023ns (routing 0.421ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.199ns (routing 0.473ns, distribution 0.726ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.023     2.028    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X52Y93         FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y93         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.067 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.462     2.529    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X42Y82         FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.199     1.861    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X42Y82         FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.037ns (37.000%)  route 0.063ns (63.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.657ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.879ns (routing 0.426ns, distribution 0.453ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.473ns, distribution 0.521ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.879     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y14         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y14         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/Q
                         net (fo=1, routed)           0.063     1.978    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[1]
    SLICE_X96Y14         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.994     1.657    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X96Y14         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.040ns (40.816%)  route 0.058ns (59.184%))
  Logic Levels:           0  
  Clock Path Skew:        -0.234ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.654ns
    Source Clock Delay      (SCD):    1.888ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.889ns (routing 0.426ns, distribution 0.463ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.473ns, distribution 0.518ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.889     1.888    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y6          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y6          FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/Q
                         net (fo=1, routed)           0.058     1.986    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[8]
    SLICE_X95Y7          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.991     1.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X95Y7          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        -0.219ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.654ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.873ns (routing 0.426ns, distribution 0.447ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.473ns, distribution 0.518ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.873     1.872    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y24         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y24         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.911 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/Q
                         net (fo=1, routed)           0.088     1.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[12]
    SLICE_X96Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.991     1.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X96Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        -0.218ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.660ns
    Source Clock Delay      (SCD):    1.877ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.878ns (routing 0.426ns, distribution 0.452ns)
  Clock Net Delay (Destination): 0.997ns (routing 0.473ns, distribution 0.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.878     1.877    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y15         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y15         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/Q
                         net (fo=1, routed)           0.088     2.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[3]
    SLICE_X96Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.997     1.660    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X96Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.231ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.654ns
    Source Clock Delay      (SCD):    1.885ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.885ns (routing 0.426ns, distribution 0.459ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.473ns, distribution 0.518ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.885     1.885    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y7          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y7          FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.925 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/Q
                         net (fo=1, routed)           0.080     2.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[0]
    SLICE_X95Y7          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.991     1.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X95Y7          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.040ns (31.008%)  route 0.089ns (68.992%))
  Logic Levels:           0  
  Clock Path Skew:        -0.219ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.658ns
    Source Clock Delay      (SCD):    1.876ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.877ns (routing 0.426ns, distribution 0.451ns)
  Clock Net Delay (Destination): 0.995ns (routing 0.473ns, distribution 0.522ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.877     1.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X92Y6          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y6          FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/Q
                         net (fo=1, routed)           0.089     2.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[4]
    SLICE_X93Y6          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.995     1.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X93Y6          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.544%)  route 0.089ns (69.456%))
  Logic Levels:           0  
  Clock Path Skew:        -0.210ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.668ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.879ns (routing 0.426ns, distribution 0.453ns)
  Clock Net Delay (Destination): 1.006ns (routing 0.473ns, distribution 0.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.879     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y14         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y14         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/Q
                         net (fo=2, routed)           0.089     2.006    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/D[0]
    SLICE_X95Y13         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.006     1.668    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X95Y13         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.654ns
    Source Clock Delay      (SCD):    1.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.876ns (routing 0.426ns, distribution 0.450ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.473ns, distribution 0.518ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.876     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y20         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y20         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/Q
                         net (fo=1, routed)           0.093     2.007    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[6]
    SLICE_X96Y20         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.991     1.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X96Y20         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.221ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.657ns
    Source Clock Delay      (SCD):    1.877ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.878ns (routing 0.426ns, distribution 0.452ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.473ns, distribution 0.521ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.878     1.877    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y15         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y15         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/Q
                         net (fo=1, routed)           0.093     2.009    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[2]
    SLICE_X96Y15         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.994     1.657    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X96Y15         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.038ns (29.008%)  route 0.093ns (70.992%))
  Logic Levels:           0  
  Clock Path Skew:        -0.221ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.658ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.879ns (routing 0.426ns, distribution 0.453ns)
  Clock Net Delay (Destination): 0.995ns (routing 0.473ns, distribution 0.522ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     0.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.879     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y14         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y14         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/Q
                         net (fo=1, routed)           0.093     2.009    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[7]
    SLICE_X96Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.995     1.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X96Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay           115 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.040ns (41.667%)  route 0.056ns (58.333%))
  Logic Levels:           0  
  Clock Path Skew:        -0.235ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.644ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.863ns (routing 0.421ns, distribution 0.442ns)
  Clock Net Delay (Destination): 0.981ns (routing 0.473ns, distribution 0.508ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.863     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X95Y32         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y32         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.918 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/Q
                         net (fo=1, routed)           0.056     1.974    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[16]
    SLICE_X95Y31         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.981     1.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X95Y31         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.040ns (40.816%)  route 0.058ns (59.184%))
  Logic Levels:           0  
  Clock Path Skew:        -0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.863ns (routing 0.421ns, distribution 0.442ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.473ns, distribution 0.517ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.863     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y26         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.918 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[1]/Q
                         net (fo=1, routed)           0.058     1.976    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[1]
    SLICE_X91Y27         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.990     1.652    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X91Y27         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_addr_strobe_lvl_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.041ns (38.432%)  route 0.066ns (61.568%))
  Logic Levels:           0  
  Clock Path Skew:        -0.218ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.667ns
    Source Clock Delay      (SCD):    1.885ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.870ns (routing 0.421ns, distribution 0.449ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.473ns, distribution 0.532ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.870     1.885    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X95Y54         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_addr_strobe_lvl_riuclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y54         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_addr_strobe_lvl_riuclk_reg/Q
                         net (fo=2, routed)           0.066     1.992    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/D[0]
    SLICE_X95Y52         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.005     1.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X95Y52         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.238ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.641ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.863ns (routing 0.421ns, distribution 0.442ns)
  Clock Net Delay (Destination): 0.978ns (routing 0.473ns, distribution 0.505ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.863     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X95Y32         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y32         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/Q
                         net (fo=1, routed)           0.075     1.992    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[10]
    SLICE_X95Y32         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.978     1.641    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X95Y32         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.237ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.645ns
    Source Clock Delay      (SCD):    1.881ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.866ns (routing 0.421ns, distribution 0.445ns)
  Clock Net Delay (Destination): 0.982ns (routing 0.473ns, distribution 0.509ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.866     1.881    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X95Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y26         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.920 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[8]/Q
                         net (fo=1, routed)           0.075     1.995    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[8]
    SLICE_X95Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.982     1.645    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X95Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        -0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.863ns (routing 0.421ns, distribution 0.442ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.473ns, distribution 0.517ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.863     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y26         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y26         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[0]/Q
                         net (fo=1, routed)           0.079     1.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[0]
    SLICE_X91Y27         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.990     1.652    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X91Y27         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/bisc_complete_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_bisc_complete_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.039ns (34.513%)  route 0.074ns (65.487%))
  Logic Levels:           0  
  Clock Path Skew:        -0.229ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.655ns
    Source Clock Delay      (SCD):    1.884ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.869ns (routing 0.421ns, distribution 0.448ns)
  Clock Net Delay (Destination): 0.992ns (routing 0.473ns, distribution 0.519ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.869     1.884    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X88Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/bisc_complete_riuclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y44         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/bisc_complete_riuclk_reg/Q
                         net (fo=1, routed)           0.074     1.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_bisc_complete_sync/D[0]
    SLICE_X88Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_bisc_complete_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.992     1.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_bisc_complete_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X88Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_bisc_complete_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.578%)  route 0.062ns (61.422%))
  Logic Levels:           0  
  Clock Path Skew:        -0.229ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.669ns
    Source Clock Delay      (SCD):    1.897ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.882ns (routing 0.421ns, distribution 0.461ns)
  Clock Net Delay (Destination): 1.006ns (routing 0.473ns, distribution 0.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.882     1.897    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y55         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y55         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.936 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[3]/Q
                         net (fo=2, routed)           0.062     1.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/phy2clb_phy_rdy_upp_riuclk[3]
    SLICE_X81Y54         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.006     1.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y54         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.038ns (30.894%)  route 0.085ns (69.106%))
  Logic Levels:           0  
  Clock Path Skew:        -0.232ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.863ns (routing 0.421ns, distribution 0.442ns)
  Clock Net Delay (Destination): 0.984ns (routing 0.473ns, distribution 0.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.863     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X96Y34         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y34         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[14]/Q
                         net (fo=1, routed)           0.085     2.001    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[14]
    SLICE_X96Y34         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.984     1.647    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X96Y34         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[14].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        -0.235ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.641ns
    Source Clock Delay      (SCD):    1.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.860ns (routing 0.421ns, distribution 0.439ns)
  Clock Net Delay (Destination): 0.978ns (routing 0.473ns, distribution 0.505ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.860     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y30         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y30         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/Q
                         net (fo=1, routed)           0.088     2.002    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[12]
    SLICE_X93Y30         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.644    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.663 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.978     1.641    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X93Y30         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Max Delay            78 Endpoints
Min Delay            86 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.718ns  (logic 0.292ns (40.669%)  route 0.426ns (59.331%))
  Logic Levels:           0  
  Clock Path Skew:        -6.921ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.157ns
    Source Clock Delay      (SCD):    10.078ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.665ns (routing 1.824ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.702ns, distribution 0.703ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.665    10.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X96Y5          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y5          RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292    10.370 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/O
                         net (fo=1, routed)           0.426    10.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[2]
    SLICE_X96Y6          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.405     3.157    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y6          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.656ns  (logic 0.288ns (43.902%)  route 0.368ns (56.098%))
  Logic Levels:           0  
  Clock Path Skew:        -6.912ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.166ns
    Source Clock Delay      (SCD):    10.078ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.665ns (routing 1.824ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.413ns (routing 0.702ns, distribution 0.711ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.665    10.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X96Y5          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y5          RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288    10.366 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/O
                         net (fo=1, routed)           0.368    10.734    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[4]
    SLICE_X94Y5          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.413     3.166    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X94Y5          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.571ns  (logic 0.281ns (49.212%)  route 0.290ns (50.788%))
  Logic Levels:           0  
  Clock Path Skew:        -6.924ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns
    Source Clock Delay      (SCD):    10.149ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.736ns (routing 1.824ns, distribution 0.912ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.702ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.736    10.149    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/WCLK
    SLICE_X97Y4          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y4          RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281    10.430 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/O
                         net (fo=1, routed)           0.290    10.720    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[15]
    SLICE_X97Y4          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473     3.225    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X97Y4          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.639ns  (logic 0.304ns (47.574%)  route 0.335ns (52.426%))
  Logic Levels:           0  
  Clock Path Skew:        -6.912ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.166ns
    Source Clock Delay      (SCD):    10.078ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.665ns (routing 1.824ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.413ns (routing 0.702ns, distribution 0.711ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.665    10.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X96Y5          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y5          RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304    10.382 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF_D1/O
                         net (fo=1, routed)           0.335    10.717    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[11]
    SLICE_X94Y5          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.413     3.166    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X94Y5          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.637ns  (logic 0.305ns (47.881%)  route 0.332ns (52.119%))
  Logic Levels:           0  
  Clock Path Skew:        -6.922ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.156ns
    Source Clock Delay      (SCD):    10.078ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.665ns (routing 1.824ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.702ns, distribution 0.702ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.665    10.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X96Y5          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y5          RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305    10.383 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/O
                         net (fo=1, routed)           0.332    10.715    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[1]
    SLICE_X95Y7          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.404     3.156    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X95Y7          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.631ns  (logic 0.287ns (45.483%)  route 0.344ns (54.517%))
  Logic Levels:           0  
  Clock Path Skew:        -6.921ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.157ns
    Source Clock Delay      (SCD):    10.078ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.665ns (routing 1.824ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.702ns, distribution 0.703ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.665    10.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X96Y5          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y5          RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287    10.365 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/O
                         net (fo=1, routed)           0.344    10.709    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[6]
    SLICE_X96Y6          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.405     3.157    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y6          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.588ns  (logic 0.079ns (13.435%)  route 0.509ns (86.565%))
  Logic Levels:           0  
  Clock Path Skew:        -6.884ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.223ns
    Source Clock Delay      (SCD):    10.107ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.694ns (routing 1.824ns, distribution 0.870ns)
  Clock Net Delay (Destination): 1.471ns (routing 0.702ns, distribution 0.769ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.694    10.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X97Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079    10.186 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          0.509    10.695    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X101Y3         FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.471     3.223    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X101Y3         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.588ns  (logic 0.079ns (13.435%)  route 0.509ns (86.565%))
  Logic Levels:           0  
  Clock Path Skew:        -6.884ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.223ns
    Source Clock Delay      (SCD):    10.107ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.694ns (routing 1.824ns, distribution 0.870ns)
  Clock Net Delay (Destination): 1.471ns (routing 0.702ns, distribution 0.769ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.694    10.107    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X97Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y14         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079    10.186 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          0.509    10.695    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X101Y3         FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.471     3.223    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X101Y3         FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.570ns  (logic 0.080ns (14.041%)  route 0.490ns (85.959%))
  Logic Levels:           0  
  Clock Path Skew:        -6.893ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.223ns
    Source Clock Delay      (SCD):    10.116ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.703ns (routing 1.824ns, distribution 0.879ns)
  Clock Net Delay (Destination): 1.471ns (routing 0.702ns, distribution 0.769ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.703    10.116    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y16         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080    10.196 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/Q
                         net (fo=25, routed)          0.490    10.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[17]
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.471     3.223    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X99Y13         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[17]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.536ns  (logic 0.295ns (55.037%)  route 0.241ns (44.963%))
  Logic Levels:           0  
  Clock Path Skew:        -6.924ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.225ns
    Source Clock Delay      (SCD):    10.149ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.736ns (routing 1.824ns, distribution 0.912ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.702ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.085     7.385    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.736    10.149    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/WCLK
    SLICE_X97Y4          RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y4          RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295    10.444 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/O
                         net (fo=1, routed)           0.241    10.685    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[14]
    SLICE_X97Y4          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.208     1.728    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.473     3.225    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X97Y4          FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.040ns (40.127%)  route 0.060ns (59.873%))
  Logic Levels:           0  
  Clock Path Skew:        -1.889ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.690ns
    Source Clock Delay      (SCD):    3.579ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.486ns (routing 0.999ns, distribution 0.487ns)
  Clock Net Delay (Destination): 1.033ns (routing 0.477ns, distribution 0.556ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.486     3.579    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y15         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y15         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.619 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp_reg/Q
                         net (fo=19, routed)          0.060     3.679    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp
    SLICE_X98Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.033     1.690    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y14         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.355%)  route 0.063ns (61.646%))
  Logic Levels:           0  
  Clock Path Skew:        -1.890ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.690ns
    Source Clock Delay      (SCD):    3.580ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.487ns (routing 0.999ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.033ns (routing 0.477ns, distribution 0.556ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.487     3.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y16         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.619 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/Q
                         net (fo=2, routed)           0.063     3.681    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[5]
    SLICE_X98Y15         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.033     1.690    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y15         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[5]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -1.881ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    3.583ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.490ns (routing 0.999ns, distribution 0.491ns)
  Clock Net Delay (Destination): 1.044ns (routing 0.477ns, distribution 0.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.490     3.583    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y16         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.622 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/Q
                         net (fo=2, routed)           0.060     3.681    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[9]
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.044     1.701    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[9]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.053%)  route 0.056ns (58.947%))
  Logic Levels:           0  
  Clock Path Skew:        -1.878ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    3.587ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.999ns, distribution 0.495ns)
  Clock Net Delay (Destination): 1.053ns (routing 0.477ns, distribution 0.576ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.494     3.587    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y14        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.626 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/Q
                         net (fo=2, routed)           0.056     3.682    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[23]
    SLICE_X102Y13        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.053     1.709    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X102Y13        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.040ns (37.146%)  route 0.068ns (62.854%))
  Logic Levels:           0  
  Clock Path Skew:        -1.879ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.696ns
    Source Clock Delay      (SCD):    3.575ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.482ns (routing 0.999ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.039ns (routing 0.477ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.482     3.575    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y17         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     3.615 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.068     3.683    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[1]
    SLICE_X98Y18         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.039     1.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y18         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.040ns (38.579%)  route 0.064ns (61.421%))
  Logic Levels:           0  
  Clock Path Skew:        -1.878ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    3.580ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.487ns (routing 0.999ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.044ns (routing 0.477ns, distribution 0.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.487     3.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y16         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     3.620 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/Q
                         net (fo=2, routed)           0.064     3.683    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[10]
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.044     1.701    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.041ns (39.544%)  route 0.063ns (60.456%))
  Logic Levels:           0  
  Clock Path Skew:        -1.878ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    3.580ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.487ns (routing 0.999ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.044ns (routing 0.477ns, distribution 0.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.487     3.580    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X98Y16         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y16         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.621 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/Q
                         net (fo=2, routed)           0.063     3.683    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[13]
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.044     1.701    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y17         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.040ns (40.404%)  route 0.059ns (59.596%))
  Logic Levels:           0  
  Clock Path Skew:        -1.893ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    3.588ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.495ns (routing 0.999ns, distribution 0.496ns)
  Clock Net Delay (Destination): 1.038ns (routing 0.477ns, distribution 0.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.495     3.588    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X100Y18        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y18        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     3.628 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.059     3.687    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in[1]
    SLICE_X100Y17        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.038     1.695    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X100Y17        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        -1.882ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.705ns
    Source Clock Delay      (SCD):    3.587ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.999ns, distribution 0.495ns)
  Clock Net Delay (Destination): 1.049ns (routing 0.477ns, distribution 0.572ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.494     3.587    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y14        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.626 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/Q
                         net (fo=2, routed)           0.062     3.688    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[20]
    SLICE_X102Y13        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.049     1.705    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X102Y13        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[20]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.041ns (39.635%)  route 0.062ns (60.365%))
  Logic Levels:           0  
  Clock Path Skew:        -1.878ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    3.587ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.999ns, distribution 0.495ns)
  Clock Net Delay (Destination): 1.053ns (routing 0.477ns, distribution 0.576ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.611     2.076    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.494     3.587    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X102Y14        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y14        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.628 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/Q
                         net (fo=2, routed)           0.062     3.690    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[15]
    SLICE_X102Y13        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.053     1.709    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X102Y13        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Max Delay             0 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.449%)  route 0.068ns (63.551%))
  Logic Levels:           0  
  Clock Path Skew:        -0.224ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.663ns
    Source Clock Delay      (SCD):    1.887ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.881ns (routing 0.421ns, distribution 0.460ns)
  Clock Net Delay (Destination): 1.006ns (routing 0.477ns, distribution 0.529ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.881     1.887    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y10         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.068     1.994    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X96Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.006     1.663    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y10         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.228ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.655ns
    Source Clock Delay      (SCD):    1.883ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.877ns (routing 0.421ns, distribution 0.456ns)
  Clock Net Delay (Destination): 0.998ns (routing 0.477ns, distribution 0.521ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.877     1.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y12         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.081     2.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.998     1.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.135ns  (logic 0.041ns (30.370%)  route 0.094ns (69.630%))
  Logic Levels:           0  
  Clock Path Skew:        -0.221ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.658ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.873ns (routing 0.421ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.001ns (routing 0.477ns, distribution 0.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.873     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y12         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.919 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.094     2.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.001     1.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.467%)  route 0.098ns (71.533%))
  Logic Levels:           0  
  Clock Path Skew:        -0.221ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.658ns
    Source Clock Delay      (SCD):    1.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.873ns (routing 0.421ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.001ns (routing 0.477ns, distribution 0.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.873     1.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y12         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.098     2.015    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.001     1.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.041ns (30.147%)  route 0.095ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        -0.228ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.655ns
    Source Clock Delay      (SCD):    1.883ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.877ns (routing 0.421ns, distribution 0.456ns)
  Clock Net Delay (Destination): 0.998ns (routing 0.477ns, distribution 0.521ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.877     1.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y12         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.924 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.095     2.019    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         0.998     1.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.039ns (25.309%)  route 0.115ns (74.691%))
  Logic Levels:           0  
  Clock Path Skew:        -0.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.661ns
    Source Clock Delay      (SCD):    1.883ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.878ns (routing 0.421ns, distribution 0.457ns)
  Clock Net Delay (Destination): 1.004ns (routing 0.477ns, distribution 0.527ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.878     1.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X93Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y2          FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.922 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.115     2.037    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.004     1.661    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.224%)  route 0.122ns (75.776%))
  Logic Levels:           0  
  Clock Path Skew:        -0.223ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.664ns
    Source Clock Delay      (SCD):    1.887ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.882ns (routing 0.421ns, distribution 0.461ns)
  Clock Net Delay (Destination): 1.008ns (routing 0.477ns, distribution 0.531ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.882     1.887    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.122     2.048    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X95Y9          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.008     1.664    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y9          FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.040ns (21.858%)  route 0.143ns (78.142%))
  Logic Levels:           0  
  Clock Path Skew:        -0.225ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.662ns
    Source Clock Delay      (SCD):    1.887ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.882ns (routing 0.421ns, distribution 0.461ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.477ns, distribution 0.528ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.882     1.887    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.143     2.070    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.005     1.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.040ns (21.164%)  route 0.149ns (78.836%))
  Logic Levels:           0  
  Clock Path Skew:        -0.224ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.663ns
    Source Clock Delay      (SCD):    1.887ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.882ns (routing 0.421ns, distribution 0.461ns)
  Clock Net Delay (Destination): 1.006ns (routing 0.477ns, distribution 0.529ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.882     1.887    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.149     2.076    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.006     1.663    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.209ns  (logic 0.040ns (19.139%)  route 0.169ns (80.861%))
  Logic Levels:           0  
  Clock Path Skew:        -0.225ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.662ns
    Source Clock Delay      (SCD):    1.887ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.882ns (routing 0.421ns, distribution 0.461ns)
  Clock Net Delay (Destination): 1.005ns (routing 0.477ns, distribution 0.528ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.882     1.887    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X95Y17         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y17         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.927 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.169     2.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.160     0.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y0 (CLOCK_ROOT)    net (fo=568, routed)         1.005     1.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y11         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  default_sysclk_c0_300mhz_clk_p
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.282ns  (logic 0.081ns (28.723%)  route 0.201ns (71.277%))
  Logic Levels:           0  
  Clock Path Skew:        1.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.207ns
    Source Clock Delay      (SCD):    1.772ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.739ns (routing 0.001ns, distribution 0.738ns)
  Clock Net Delay (Destination): 1.436ns (routing 0.695ns, distribution 0.741ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.739     1.772    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X84Y108        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y108        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.201     2.054    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X84Y109        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.436     3.207    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y109        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.234ns  (logic 0.081ns (34.610%)  route 0.153ns (65.390%))
  Logic Levels:           0  
  Clock Path Skew:        1.395ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.196ns
    Source Clock Delay      (SCD):    1.801ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.768ns (routing 0.001ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.425ns (routing 0.695ns, distribution 0.730ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.768     1.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y103        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     1.882 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.153     2.035    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.425     3.196    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.040ns (40.127%)  route 0.060ns (59.873%))
  Logic Levels:           0  
  Clock Path Skew:        0.649ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.689ns
    Source Clock Delay      (SCD):    1.039ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.432ns (routing 0.000ns, distribution 0.432ns)
  Clock Net Delay (Destination): 1.015ns (routing 0.473ns, distribution 0.542ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.432     1.039    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y103        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.060     1.139    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.015     1.689    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        0.668ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.694ns
    Source Clock Delay      (SCD):    1.025ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.418ns (routing 0.000ns, distribution 0.418ns)
  Clock Net Delay (Destination): 1.020ns (routing 0.473ns, distribution 0.547ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.607 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.418     1.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X84Y108        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y108        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.065 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.079     1.144    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X84Y109        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.020     1.694    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y109        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Max Delay             0 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        -0.216ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.659ns
    Source Clock Delay      (SCD):    1.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.870ns (routing 0.421ns, distribution 0.449ns)
  Clock Net Delay (Destination): 0.985ns (routing 0.473ns, distribution 0.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.870     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X92Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y44         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/Q
                         net (fo=1, routed)           0.058     1.972    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[20]
    SLICE_X92Y45         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.985     1.659    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X92Y45         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.041ns (40.722%)  route 0.060ns (59.278%))
  Logic Levels:           0  
  Clock Path Skew:        -0.205ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.670ns
    Source Clock Delay      (SCD):    1.874ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.869ns (routing 0.421ns, distribution 0.448ns)
  Clock Net Delay (Destination): 0.996ns (routing 0.473ns, distribution 0.523ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.869     1.874    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X92Y55         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y55         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/Q
                         net (fo=2, routed)           0.060     1.975    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/D[0]
    SLICE_X92Y56         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.996     1.670    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/CLK
    SLICE_X92Y56         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.654ns
    Source Clock Delay      (SCD):    1.876ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.870ns (routing 0.421ns, distribution 0.449ns)
  Clock Net Delay (Destination): 0.980ns (routing 0.473ns, distribution 0.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.870     1.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y39         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y39         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/Q
                         net (fo=1, routed)           0.081     1.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[19]
    SLICE_X91Y39         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.980     1.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y39         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.787%)  route 0.082ns (67.213%))
  Logic Levels:           0  
  Clock Path Skew:        -0.216ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.660ns
    Source Clock Delay      (SCD):    1.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.870ns (routing 0.421ns, distribution 0.449ns)
  Clock Net Delay (Destination): 0.986ns (routing 0.473ns, distribution 0.513ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.870     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X92Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y48         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/Q
                         net (fo=1, routed)           0.082     1.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[17]
    SLICE_X92Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.986     1.660    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X92Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.216ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.660ns
    Source Clock Delay      (SCD):    1.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.870ns (routing 0.421ns, distribution 0.449ns)
  Clock Net Delay (Destination): 0.986ns (routing 0.473ns, distribution 0.513ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.870     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X92Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y48         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/Q
                         net (fo=1, routed)           0.087     2.001    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[31]
    SLICE_X92Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.986     1.660    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X92Y48         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.038ns (38.775%)  route 0.060ns (61.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.213ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.694ns
    Source Clock Delay      (SCD):    1.906ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.901ns (routing 0.421ns, distribution 0.480ns)
  Clock Net Delay (Destination): 1.020ns (routing 0.473ns, distribution 0.547ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.901     1.906    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/SYNC[19].sync_reg_reg[1]
    SLICE_X93Y61         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y61         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/Q
                         net (fo=1, routed)           0.060     2.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/D[0]
    SLICE_X93Y61         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.020     1.694    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/CLK
    SLICE_X93Y61         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.039ns (28.058%)  route 0.100ns (71.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.219ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.657ns
    Source Clock Delay      (SCD):    1.876ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.870ns (routing 0.421ns, distribution 0.449ns)
  Clock Net Delay (Destination): 0.983ns (routing 0.473ns, distribution 0.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.870     1.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/SYNC[19].sync_reg_reg[1]
    SLICE_X90Y39         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y39         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/Q
                         net (fo=1, routed)           0.100     2.015    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/D[0]
    SLICE_X91Y38         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.983     1.657    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/CLK
    SLICE_X91Y38         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.153ns  (logic 0.037ns (24.183%)  route 0.116ns (75.817%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.664ns
    Source Clock Delay      (SCD):    1.876ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.871ns (routing 0.421ns, distribution 0.450ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.473ns, distribution 0.517ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.871     1.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X93Y40         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y40         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.913 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/Q
                         net (fo=1, routed)           0.116     2.029    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[26]
    SLICE_X93Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.990     1.664    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X93Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.155ns  (logic 0.039ns (25.161%)  route 0.116ns (74.839%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.664ns
    Source Clock Delay      (SCD):    1.876ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.871ns (routing 0.421ns, distribution 0.450ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.473ns, distribution 0.517ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.871     1.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X93Y40         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y40         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[16]/Q
                         net (fo=1, routed)           0.116     2.031    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[16]
    SLICE_X93Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.990     1.664    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X93Y44         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[16].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.153ns  (logic 0.038ns (24.837%)  route 0.115ns (75.163%))
  Logic Levels:           0  
  Clock Path Skew:        -0.219ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.664ns
    Source Clock Delay      (SCD):    1.883ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.878ns (routing 0.421ns, distribution 0.457ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.473ns, distribution 0.517ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.878     1.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X94Y38         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y38         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.921 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/Q
                         net (fo=1, routed)           0.115     2.036    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X94Y42         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.990     1.664    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X94Y42         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay           332 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.619ns  (logic 0.076ns (12.270%)  route 0.543ns (87.730%))
  Logic Levels:           0  
  Clock Path Skew:        0.347ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.201ns
    Source Clock Delay      (SCD):    2.854ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.620ns (routing 0.764ns, distribution 0.856ns)
  Clock Net Delay (Destination): 1.430ns (routing 0.695ns, distribution 0.735ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.620     2.854    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X86Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y102        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.930 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.543     3.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X94Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.430     3.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X94Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.367ns  (logic 0.079ns (21.526%)  route 0.288ns (78.474%))
  Logic Levels:           0  
  Clock Path Skew:        0.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.202ns
    Source Clock Delay      (SCD):    2.854ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.620ns (routing 0.764ns, distribution 0.856ns)
  Clock Net Delay (Destination): 1.431ns (routing 0.695ns, distribution 0.736ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.620     2.854    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X96Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y104        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.288     3.221    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X96Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.520 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     1.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.431     3.202    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X96Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.155ns  (logic 0.039ns (25.161%)  route 0.116ns (74.839%))
  Logic Levels:           0  
  Clock Path Skew:        -0.217ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    1.912ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.897ns (routing 0.421ns, distribution 0.476ns)
  Clock Net Delay (Destination): 1.021ns (routing 0.473ns, distribution 0.548ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.897     1.912    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X96Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y104        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.951 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.116     2.067    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X96Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.021     1.695    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X96Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.289ns  (logic 0.038ns (13.132%)  route 0.251ns (86.868%))
  Logic Levels:           0  
  Clock Path Skew:        -0.217ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.695ns
    Source Clock Delay      (SCD):    1.912ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.897ns (routing 0.421ns, distribution 0.476ns)
  Clock Net Delay (Destination): 1.021ns (routing 0.473ns, distribution 0.548ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.897     1.912    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X86Y102        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y102        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.950 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.251     2.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X94Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.021     1.695    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X94Y104        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.347ns  (logic 0.039ns (11.251%)  route 0.308ns (88.749%))
  Logic Levels:           0  
  Clock Path Skew:        -0.157ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.765ns
    Source Clock Delay      (SCD):    1.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.906ns (routing 0.421ns, distribution 0.485ns)
  Clock Net Delay (Destination): 1.091ns (routing 0.473ns, distribution 0.618ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.906     1.921    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.960 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/Q
                         net (fo=15, routed)          0.308     2.268    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[4]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.091     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.348ns  (logic 0.039ns (11.218%)  route 0.309ns (88.782%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.769ns
    Source Clock Delay      (SCD):    1.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.906ns (routing 0.421ns, distribution 0.485ns)
  Clock Net Delay (Destination): 1.095ns (routing 0.473ns, distribution 0.622ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.906     1.921    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y114        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y114        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.960 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/Q
                         net (fo=15, routed)          0.309     2.269    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[4]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.095     1.769    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.360ns  (logic 0.040ns (11.110%)  route 0.320ns (88.890%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.765ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.903ns (routing 0.421ns, distribution 0.482ns)
  Clock Net Delay (Destination): 1.091ns (routing 0.473ns, distribution 0.618ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.903     1.918    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y81         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y81         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=15, routed)          0.320     2.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[12]
    BITSLICE_CONTROL_X0Y10
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.091     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y10
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.360ns  (logic 0.040ns (11.110%)  route 0.320ns (88.890%))
  Logic Levels:           0  
  Clock Path Skew:        -0.157ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.761ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.903ns (routing 0.421ns, distribution 0.482ns)
  Clock Net Delay (Destination): 1.087ns (routing 0.473ns, distribution 0.614ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.903     1.918    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y81         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y81         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.958 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=15, routed)          0.320     2.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[12]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.087     1.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[15]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.375ns  (logic 0.039ns (10.390%)  route 0.336ns (89.610%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.765ns
    Source Clock Delay      (SCD):    1.917ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.902ns (routing 0.421ns, distribution 0.481ns)
  Clock Net Delay (Destination): 1.091ns (routing 0.473ns, distribution 0.618ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.902     1.917    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y82         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y82         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.956 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[15]/Q
                         net (fo=15, routed)          0.336     2.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[15]
    BITSLICE_CONTROL_X0Y10
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[15]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.091     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y10
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[15]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.375ns  (logic 0.039ns (10.390%)  route 0.336ns (89.610%))
  Logic Levels:           0  
  Clock Path Skew:        -0.157ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.761ns
    Source Clock Delay      (SCD):    1.917ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.902ns (routing 0.421ns, distribution 0.481ns)
  Clock Net Delay (Destination): 1.087ns (routing 0.473ns, distribution 0.614ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.902     1.917    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y82         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y82         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.956 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[15]/Q
                         net (fo=15, routed)          0.336     2.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[15]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[15]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.087     1.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.383ns  (logic 0.039ns (10.191%)  route 0.344ns (89.809%))
  Logic Levels:           0  
  Clock Path Skew:        -0.156ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.765ns
    Source Clock Delay      (SCD):    1.920ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.905ns (routing 0.421ns, distribution 0.484ns)
  Clock Net Delay (Destination): 1.091ns (routing 0.473ns, distribution 0.618ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.905     1.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y109        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y109        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.959 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=15, routed)          0.344     2.303    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[3]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.091     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.384ns  (logic 0.039ns (10.165%)  route 0.345ns (89.835%))
  Logic Levels:           0  
  Clock Path Skew:        -0.152ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.769ns
    Source Clock Delay      (SCD):    1.920ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.905ns (routing 0.421ns, distribution 0.484ns)
  Clock Net Delay (Destination): 1.095ns (routing 0.473ns, distribution 0.622ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.015 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        0.905     1.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y109        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y109        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.959 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=15, routed)          0.345     2.304    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[3]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.478 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y36         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=1657, routed)        1.095     1.769    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.881ns  (logic 0.028ns (0.972%)  route 2.853ns (99.028%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.655     7.881    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y3           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.860ns  (logic 0.028ns (0.979%)  route 2.832ns (99.021%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.634     7.860    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y2           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.853ns  (logic 0.028ns (0.981%)  route 2.825ns (99.019%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.627     7.853    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y1           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.834ns  (logic 0.028ns (0.988%)  route 2.806ns (99.012%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.608     7.834    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y0           RFADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.833ns  (logic 0.028ns (0.988%)  route 2.805ns (99.012%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.607     7.833    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y0           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.810ns  (logic 0.028ns (0.996%)  route 2.782ns (99.004%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.584     7.810    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y1           RFADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.789ns  (logic 0.028ns (1.004%)  route 2.761ns (98.996%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.563     7.789    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y2           RFADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.772ns  (logic 0.028ns (1.010%)  route 2.744ns (98.990%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.546     7.772    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y3           RFADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.497ns  (logic 0.017ns (1.136%)  route 1.480ns (98.864%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.377     1.497    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y3           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.509ns  (logic 0.017ns (1.127%)  route 1.492ns (98.873%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.389     1.509    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y2           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.522ns  (logic 0.017ns (1.117%)  route 1.505ns (98.883%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.402     1.522    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y1           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.522ns  (logic 0.017ns (1.117%)  route 1.505ns (98.883%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.402     1.522    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y0           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.535ns  (logic 0.017ns (1.107%)  route 1.518ns (98.893%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.415     1.535    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y1           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.539ns  (logic 0.017ns (1.105%)  route 1.522ns (98.895%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.419     1.539    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y0           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.548ns  (logic 0.017ns (1.098%)  route 1.531ns (98.902%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.428     1.548    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y2           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.564ns  (logic 0.017ns (1.087%)  route 1.547ns (98.913%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.444     1.564    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y3           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_sdram_c0_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.351ns  (logic 0.887ns (37.729%)  route 1.464ns (62.271%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.645ns (routing 0.764ns, distribution 0.881ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.669 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     1.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.944 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.189    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       1.645     2.862    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X87Y80         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y80         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.942 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           1.464     4.406    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    AH20                 OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.807     5.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     5.213    ddr4_sdram_c0_reset_n
    AH20                                                              r  ddr4_sdram_c0_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_sdram_c0_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.094ns  (logic 0.422ns (38.577%)  route 0.672ns (61.423%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.906ns (routing 0.421ns, distribution 0.485ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.356 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y37         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y0 (CLOCK_ROOT)    net (fo=27077, routed)       0.906     1.911    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X87Y80         FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y80         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.952 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           0.672     2.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    AH20                 OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.381     3.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     3.005    ddr4_sdram_c0_reset_n
    AH20                                                              r  ddr4_sdram_c0_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC2_CLK

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.956ns  (logic 1.278ns (32.310%)  route 2.677ns (67.690%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT6=1)
  Clock Path Skew:        3.613ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 3.069ns (routing 1.690ns, distribution 1.379ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L17                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L17                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      1.038     1.038 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.038    PMOD1_0_LS_IBUF_inst/OUT
    L17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     1.038 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.792     2.831    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X66Y230        LUT4 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     2.921 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2/O
                         net (fo=1, routed)           0.495     3.416    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2_n_0
    SLICE_X67Y242        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.566 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.390     3.956    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X79Y243        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.069     3.613    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X79Y243        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.562ns  (logic 1.130ns (31.721%)  route 2.432ns (68.279%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        3.608ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 3.064ns (routing 1.690ns, distribution 1.374ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    M17                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    M17                  INBUF (Prop_INBUF_HDIOB_M_PAD_O)
                                                      1.040     1.040 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.040    PMOD1_1_LS_IBUF_inst/OUT
    M17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_M_I_O)
                                                      0.000     1.040 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.815     2.855    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X66Y231        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.945 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[2]_i_1/O
                         net (fo=1, routed)           0.617     3.562    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[2]
    SLICE_X79Y246        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      3.064     3.608    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X79Y246        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.606ns  (logic 0.409ns (25.450%)  route 1.197ns (74.550%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        2.556ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.556ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 2.081ns (routing 1.128ns, distribution 0.953ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    M17                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    M17                  INBUF (Prop_INBUF_HDIOB_M_PAD_O)
                                                      0.374     0.374 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.374    PMOD1_1_LS_IBUF_inst/OUT
    M17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_M_I_O)
                                                      0.000     0.374 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.909     1.283    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X66Y231        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.318 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[2]_i_1/O
                         net (fo=1, routed)           0.288     1.606    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[2]
    SLICE_X79Y246        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.081     2.556    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X79Y246        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.777ns  (logic 0.467ns (26.270%)  route 1.310ns (73.730%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT6=1)
  Clock Path Skew:        2.560ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.560ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 2.085ns (routing 1.128ns, distribution 0.957ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L17                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L17                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.372     0.372 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.372    PMOD1_0_LS_IBUF_inst/OUT
    L17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.372 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.879     1.251    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X66Y230        LUT4 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.035     1.286 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2/O
                         net (fo=1, routed)           0.253     1.539    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2_n_0
    SLICE_X67Y242        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.060     1.599 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.178     1.777    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X79Y243        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=126500, routed)      2.085     2.560    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X79Y243        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             3 Endpoints
Min Delay             3 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.531ns  (logic 1.215ns (34.407%)  route 2.316ns (65.593%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT5=1)
  Clock Path Skew:        5.358ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.358ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.283ns (routing 1.400ns, distribution 0.883ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    M17                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    M17                  INBUF (Prop_INBUF_HDIOB_M_PAD_O)
                                                      1.040     1.040 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.040    PMOD1_1_LS_IBUF_inst/OUT
    M17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_M_I_O)
                                                      0.000     1.040 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.767     2.807    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X66Y231        LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.123     2.930 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2/O
                         net (fo=1, routed)           0.041     2.971    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2_n_0
    SLICE_X66Y231        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.052     3.023 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_1/O
                         net (fo=1, routed)           0.508     3.531    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[1]
    SLICE_X75Y236        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.283     5.358    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X75Y236        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.353ns  (logic 1.128ns (33.648%)  route 2.224ns (66.352%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        5.334ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.334ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.259ns (routing 1.400ns, distribution 0.859ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L17                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L17                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      1.038     1.038 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.038    PMOD1_0_LS_IBUF_inst/OUT
    L17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     1.038 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.794     2.833    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X66Y230        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.923 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1__0/O
                         net (fo=1, routed)           0.430     3.353    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[4]
    SLICE_X69Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.259     5.334    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X69Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.748ns  (logic 0.037ns (2.117%)  route 1.711ns (97.883%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.419ns (routing 1.400ns, distribution 1.019ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.645     1.645    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X82Y329        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     1.682 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.066     1.748    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X82Y329        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       2.023     2.205    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.835 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.051    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.075 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        2.419     5.494    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X82Y329        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.887ns  (logic 0.014ns (1.578%)  route 0.873ns (98.422%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.690ns (routing 0.950ns, distribution 0.740ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.849     0.849    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X82Y329        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     0.863 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.024     0.887    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X82Y329        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.690     3.112    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X82Y329        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.475ns  (logic 0.407ns (27.581%)  route 1.068ns (72.419%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        2.996ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.996ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.574ns (routing 0.950ns, distribution 0.624ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L17                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L17                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.372     0.372 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.372    PMOD1_0_LS_IBUF_inst/OUT
    L17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.372 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.879     1.251    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X66Y230        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.286 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1__0/O
                         net (fo=1, routed)           0.189     1.475    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[4]
    SLICE_X69Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.574     2.996    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X69Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.593ns  (logic 0.446ns (27.980%)  route 1.147ns (72.020%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT5=1)
  Clock Path Skew:        3.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.011ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.589ns (routing 0.950ns, distribution 0.639ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    M17                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    M17                  INBUF (Prop_INBUF_HDIOB_M_PAD_O)
                                                      0.374     0.374 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.374    PMOD1_1_LS_IBUF_inst/OUT
    M17                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_M_I_O)
                                                      0.000     0.374 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.890     1.264    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X66Y231        LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.050     1.314 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2/O
                         net (fo=1, routed)           0.023     1.337    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2_n_0
    SLICE_X66Y231        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.022     1.359 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_1/O
                         net (fo=1, routed)           0.234     1.593    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[1]
    SLICE_X75Y236        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=53450, routed)       1.385     1.532    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.237 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.403    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.422 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=4247, routed)        1.589     3.011    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X75Y236        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay            15 Endpoints
Min Delay            15 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[22]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.537ns  (logic 0.653ns (14.391%)  route 3.884ns (85.609%))
  Logic Levels:           6  (LUT5=1 LUT6=4 MUXF7=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[22]
                         net (fo=2, routed)           3.039     3.039    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[22]
    SLICE_X109Y188       LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.149     3.188 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_111/O
                         net (fo=1, routed)           0.096     3.284    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_111_n_0
    SLICE_X109Y188       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     3.372 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_73/O
                         net (fo=1, routed)           0.025     3.397    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_73_n_0
    SLICE_X109Y188       MUXF7 (Prop_F7MUX_CD_SLICEM_I0_O)
                                                      0.069     3.466 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[0]_i_36/O
                         net (fo=1, routed)           0.232     3.698    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[0]_i_36_n_0
    SLICE_X110Y192       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.150     3.848 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_11/O
                         net (fo=1, routed)           0.045     3.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_11_n_0
    SLICE_X110Y192       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.098     3.991 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_3/O
                         net (fo=1, routed)           0.398     4.389    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_3_n_0
    SLICE_X108Y176       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     4.488 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.049     4.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X108Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.232ns  (logic 0.276ns (6.521%)  route 3.956ns (93.479%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           3.323     3.323    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[1]
    SLICE_X108Y192       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     3.358 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_76/O
                         net (fo=1, routed)           0.044     3.402    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_76_n_0
    SLICE_X108Y192       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.051     3.453 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_35/O
                         net (fo=1, routed)           0.207     3.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_35_n_0
    SLICE_X110Y192       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.051     3.711 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_13/O
                         net (fo=1, routed)           0.039     3.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_13_n_0
    SLICE_X110Y192       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.089     3.839 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_3/O
                         net (fo=1, routed)           0.294     4.133    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_3_n_0
    SLICE_X108Y179       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     4.183 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.049     4.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X108Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[23]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.131ns  (logic 0.284ns (6.875%)  route 3.847ns (93.125%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.209ns (routing 0.691ns, distribution 1.518ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[23]
                         net (fo=1, routed)           3.058     3.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[23]
    SLICE_X106Y191       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     3.094 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_23/O
                         net (fo=1, routed)           0.337     3.431    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_23_n_0
    SLICE_X104Y189       LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.125     3.556 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6/O
                         net (fo=1, routed)           0.386     3.942    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_n_0
    SLICE_X103Y179       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.123     4.065 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_1/O
                         net (fo=1, routed)           0.066     4.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_59
    SLICE_X103Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.209     2.391    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.901ns  (logic 0.411ns (10.536%)  route 3.490ns (89.464%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.252ns (routing 0.691ns, distribution 1.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[3]
                         net (fo=1, routed)           2.739     2.739    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[3]
    SLICE_X108Y192       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.051     2.790 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_60/O
                         net (fo=1, routed)           0.089     2.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_60_n_0
    SLICE_X108Y192       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     2.914 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_26/O
                         net (fo=1, routed)           0.113     3.027    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_26_n_0
    SLICE_X109Y192       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.150     3.177 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10/O
                         net (fo=1, routed)           0.217     3.394    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10_n_0
    SLICE_X108Y186       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     3.518 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/O
                         net (fo=1, routed)           0.283     3.801    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2_n_0
    SLICE_X108Y176       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.051     3.852 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.049     3.901    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X108Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.252     2.434    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y176       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.827ns  (logic 0.413ns (10.792%)  route 3.414ns (89.208%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.691ns, distribution 1.550ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           2.279     2.279    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[4]
    SLICE_X108Y195       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.124     2.403 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_50/O
                         net (fo=1, routed)           0.469     2.872    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_50_n_0
    SLICE_X107Y190       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.090     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_23/O
                         net (fo=1, routed)           0.131     3.093    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_23_n_0
    SLICE_X107Y189       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051     3.144 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_6/O
                         net (fo=1, routed)           0.486     3.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_6_n_0
    SLICE_X108Y182       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.148     3.778 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.049     3.827    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_78
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[21]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.709ns  (logic 0.189ns (5.096%)  route 3.520ns (94.904%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.209ns (routing 0.691ns, distribution 1.518ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[21]
                         net (fo=1, routed)           3.076     3.076    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[21]
    SLICE_X105Y194       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     3.126 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_11/O
                         net (fo=1, routed)           0.083     3.209    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_11_n_0
    SLICE_X104Y194       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     3.260 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_6/O
                         net (fo=1, routed)           0.295     3.555    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_6_n_0
    SLICE_X103Y177       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.088     3.643 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_1/O
                         net (fo=1, routed)           0.066     3.709    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_61
    SLICE_X103Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.209     2.391    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[16]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.689ns  (logic 0.260ns (7.048%)  route 3.429ns (92.952%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.194ns (routing 0.691ns, distribution 1.503ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[16]
                         net (fo=1, routed)           2.793     2.793    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[16]
    SLICE_X106Y193       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     2.829 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_7/O
                         net (fo=1, routed)           0.331     3.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_7_n_0
    SLICE_X104Y190       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     3.285 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_2/O
                         net (fo=1, routed)           0.256     3.541    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_2_n_0
    SLICE_X102Y179       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     3.640 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_1/O
                         net (fo=1, routed)           0.049     3.689    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_66
    SLICE_X102Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.194     2.376    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[19]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.677ns  (logic 0.235ns (6.391%)  route 3.442ns (93.609%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[19]
                         net (fo=1, routed)           3.001     3.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[19]
    SLICE_X105Y192       LUT4 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     3.037 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_22/O
                         net (fo=1, routed)           0.056     3.093    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_22_n_0
    SLICE_X105Y192       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.148     3.241 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_6/O
                         net (fo=1, routed)           0.336     3.577    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_6_n_0
    SLICE_X106Y179       LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.051     3.628 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_1/O
                         net (fo=1, routed)           0.049     3.677    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_63
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[18]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.555ns  (logic 0.271ns (7.623%)  route 3.284ns (92.377%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.222ns (routing 0.691ns, distribution 1.531ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[18]
                         net (fo=1, routed)           2.656     2.656    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[18]
    SLICE_X106Y193       LUT4 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     2.691 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_7/O
                         net (fo=1, routed)           0.178     2.869    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_7_n_0
    SLICE_X105Y191       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.090     2.959 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_2/O
                         net (fo=1, routed)           0.400     3.359    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_2_n_0
    SLICE_X106Y179       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     3.505 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_1/O
                         net (fo=1, routed)           0.050     3.555    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_64
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.222     2.404    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[20]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.531ns  (logic 0.235ns (6.655%)  route 3.296ns (93.345%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.192ns (routing 0.691ns, distribution 1.501ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[20]
                         net (fo=1, routed)           2.706     2.706    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[20]
    SLICE_X105Y194       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     2.742 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_14/O
                         net (fo=1, routed)           0.087     2.829    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_14_n_0
    SLICE_X104Y194       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     2.882 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_3/O
                         net (fo=1, routed)           0.453     3.335    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_3_n_0
    SLICE_X102Y180       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     3.481 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_1/O
                         net (fo=1, routed)           0.050     3.531    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_62
    SLICE_X102Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       2.192     2.374    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[21]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.573ns  (logic 0.028ns (4.887%)  route 0.545ns (95.113%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.524ns (routing 0.463ns, distribution 1.061ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[21]
                         net (fo=1, routed)           0.371     0.371    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[21]
    SLICE_X102Y162       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.014     0.385 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_4/O
                         net (fo=1, routed)           0.150     0.535    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_4_n_0
    SLICE_X103Y177       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.014     0.549 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_1/O
                         net (fo=1, routed)           0.024     0.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_61
    SLICE_X103Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.524     1.671    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y177       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[23]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.609ns  (logic 0.036ns (5.911%)  route 0.573ns (94.089%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.524ns (routing 0.463ns, distribution 1.061ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[23]
                         net (fo=1, routed)           0.508     0.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[23]
    SLICE_X103Y179       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.014     0.522 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_4/O
                         net (fo=1, routed)           0.041     0.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_4_n_0
    SLICE_X103Y179       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.022     0.585 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_1/O
                         net (fo=1, routed)           0.024     0.609    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_59
    SLICE_X103Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.524     1.671    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[17]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.611ns  (logic 0.037ns (6.056%)  route 0.574ns (93.944%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.503ns (routing 0.463ns, distribution 1.040ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[17]
                         net (fo=1, routed)           0.496     0.496    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[17]
    SLICE_X102Y180       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.015     0.511 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_4/O
                         net (fo=1, routed)           0.062     0.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_4_n_0
    SLICE_X102Y180       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     0.595 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_1/O
                         net (fo=1, routed)           0.016     0.611    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_65
    SLICE_X102Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.503     1.650    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[16]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.627ns  (logic 0.045ns (7.177%)  route 0.582ns (92.823%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.510ns (routing 0.463ns, distribution 1.047ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[16]
                         net (fo=1, routed)           0.526     0.526    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[16]
    SLICE_X102Y179       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.023     0.549 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_4/O
                         net (fo=1, routed)           0.040     0.589    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_4_n_0
    SLICE_X102Y179       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     0.611 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_1/O
                         net (fo=1, routed)           0.016     0.627    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_66
    SLICE_X102Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.510     1.657    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[20]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.632ns  (logic 0.064ns (10.127%)  route 0.568ns (89.873%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.503ns (routing 0.463ns, distribution 1.040ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[20]
                         net (fo=1, routed)           0.522     0.522    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[20]
    SLICE_X102Y180       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014     0.536 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_4/O
                         net (fo=1, routed)           0.029     0.565    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_4_n_0
    SLICE_X102Y180       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     0.615 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_1/O
                         net (fo=1, routed)           0.017     0.632    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_62
    SLICE_X102Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.503     1.650    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[22]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.643ns  (logic 0.082ns (12.758%)  route 0.561ns (87.242%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.524ns (routing 0.463ns, distribution 1.061ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[22]
                         net (fo=2, routed)           0.380     0.380    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[22]
    SLICE_X102Y161       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.060     0.440 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_5/O
                         net (fo=1, routed)           0.155     0.595    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_5_n_0
    SLICE_X103Y179       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.022     0.617 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_1/O
                         net (fo=1, routed)           0.026     0.643    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_60
    SLICE_X103Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.524     1.671    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.660ns  (logic 0.086ns (13.026%)  route 0.574ns (86.974%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.534ns (routing 0.463ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[2]
                         net (fo=2, routed)           0.295     0.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[2]
    SLICE_X108Y158       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.050     0.345 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_18/O
                         net (fo=1, routed)           0.100     0.445    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_18_n_0
    SLICE_X108Y163       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.022     0.467 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_4/O
                         net (fo=1, routed)           0.162     0.629    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_4_n_0
    SLICE_X108Y184       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.014     0.643 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.017     0.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X108Y184       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.534     1.681    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y184       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.682ns  (logic 0.073ns (10.704%)  route 0.609ns (89.296%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.533ns (routing 0.463ns, distribution 1.070ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.313     0.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[7]
    SLICE_X111Y179       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.014     0.327 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36/O
                         net (fo=1, routed)           0.079     0.406    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36_n_0
    SLICE_X109Y179       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     0.421 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_12/O
                         net (fo=1, routed)           0.072     0.493    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_12_n_0
    SLICE_X109Y179       LUT5 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     0.515 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                         net (fo=1, routed)           0.128     0.643    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    SLICE_X108Y185       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.022     0.665 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.017     0.682    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y185       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.533     1.680    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y185       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[18]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.699ns  (logic 0.099ns (14.163%)  route 0.600ns (85.837%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[18]
                         net (fo=1, routed)           0.476     0.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[18]
    SLICE_X107Y179       LUT5 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.035     0.511 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_13/O
                         net (fo=1, routed)           0.078     0.589    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_13_n_0
    SLICE_X106Y179       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.014     0.603 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_4/O
                         net (fo=1, routed)           0.029     0.632    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_4_n_0
    SLICE_X106Y179       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     0.682 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[18]_i_1/O
                         net (fo=1, routed)           0.017     0.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_64
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[19]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.744ns  (logic 0.130ns (17.473%)  route 0.614ns (82.527%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.528ns (routing 0.463ns, distribution 1.065ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[19]
                         net (fo=1, routed)           0.501     0.501    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_1[19]
    SLICE_X107Y179       LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.035     0.536 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_7/O
                         net (fo=1, routed)           0.068     0.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_7_n_0
    SLICE_X106Y179       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     0.639 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_2/O
                         net (fo=1, routed)           0.030     0.669    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_2_n_0
    SLICE_X106Y179       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.060     0.729 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_1/O
                         net (fo=1, routed)           0.015     0.744    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_63
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y63        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=53450, routed)       1.528     1.675    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.608ns  (logic 4.424ns (78.894%)  route 1.184ns (21.106%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.397ns (routing 1.653ns, distribution 0.744ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.136     5.436    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X100Y26        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.124     5.560 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.048     5.608    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X100Y26        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.397     4.925    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y26        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.565ns  (logic 4.300ns (77.275%)  route 1.265ns (22.725%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.397ns (routing 1.653ns, distribution 0.744ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.265     5.565    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X99Y24         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.397     4.925    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X99Y24         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.534ns  (logic 4.352ns (78.648%)  route 1.182ns (21.352%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.403ns (routing 1.653ns, distribution 0.750ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.123     5.423    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X103Y25        LUT4 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.052     5.475 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.059     5.534    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X103Y25        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.403     4.931    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X103Y25        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.317ns  (logic 4.353ns (81.869%)  route 0.964ns (18.131%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.401ns (routing 1.653ns, distribution 0.748ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.911     5.211    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X103Y32        LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.053     5.264 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.053     5.317    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X103Y32        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.039     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.528 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         2.401     4.929    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X103Y32        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.984ns  (logic 0.488ns (49.593%)  route 0.496ns (50.407%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.685ns (routing 1.125ns, distribution 0.560ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.478     0.943    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X103Y32        LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     0.966 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.018     0.984    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X103Y32        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.685     8.130    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X103Y32        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.082ns  (logic 0.487ns (45.000%)  route 0.595ns (55.000%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.685ns (routing 1.125ns, distribution 0.560ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.574     1.039    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X103Y25        LUT4 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.022     1.061 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.021     1.082    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X103Y25        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.685     8.130    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X103Y25        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.083ns  (logic 0.465ns (42.928%)  route 0.618ns (57.072%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.679ns (routing 1.125ns, distribution 0.554ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.618     1.083    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X99Y24         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.679     8.124    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X99Y24         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.115ns  (logic 0.515ns (46.179%)  route 0.600ns (53.821%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.679ns (routing 1.125ns, distribution 0.554ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.584     1.049    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X100Y26        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     1.099 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.016     1.115    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X100Y26        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.126     6.426    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y164        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.679     8.124    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y26        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  default_sysclk_c0_300mhz_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.147ns  (logic 0.176ns (8.197%)  route 1.971ns (91.803%))
  Logic Levels:           2  (LUT2=1 LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.673ns (routing 0.001ns, distribution 0.672ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLL_X0Y0             PLLE4_ADV                    0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                         net (fo=1, routed)           0.889     0.889    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_i[0]
    SLICE_X81Y85         LUT2 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.035     0.924 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_INST_0/O
                         net (fo=1, routed)           0.434     1.358    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/pll_lock
    SLICE_X81Y107        LUT3 (Prop_B5LUT_SLICEL_I2_O)
                                                      0.141     1.499 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.648     2.147    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.841    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.865 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.673     1.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.629ns  (logic 0.090ns (14.309%)  route 0.539ns (85.691%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.646ns (routing 0.001ns, distribution 0.645ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.310     0.310    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y107        LUT2 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.090     0.400 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.229     0.629    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X84Y108        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.501 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.541    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.841    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.865 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.646     1.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X84Y108        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.288ns  (logic 0.036ns (12.495%)  route 0.252ns (87.505%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.477ns (routing 0.001ns, distribution 0.476ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.157     0.157    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y107        LUT2 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.036     0.193 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.095     0.288    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X84Y108        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.477     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X84Y108        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.481ns  (logic 0.033ns (6.859%)  route 0.448ns (93.141%))
  Logic Levels:           1  (LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.493ns (routing 0.001ns, distribution 0.492ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.157     0.157    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y107        LUT3 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.033     0.190 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.291     0.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.526    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.780 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.493     1.273    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X95Y103        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C





